Uartx_Iir Registers - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

UARTx_IIR Registers

When cleared, the
field indicates the highest priority pending interrupt. The receive line
TUS
status has the highest priority; the
est priority. In the case where both interrupts are signalling, the
reads 0x06.
When a UART interrupt is pending, the interrupt service routine (ISR)
needs to clear the interrupt latch explicitly.
clear any of the three latches.
UART Interrupt Identification Registers (UARTx_IIR)
RO
15 14 13 12 11 10
0 0
UART0:
0xFFC0 0408
UART1:
0xFFC0 2008
STATUS[1:0]
00 - Reserved
01 - UARTx_THR empty. Write UARTx_THR or read UARTx_IIR to clear
interrupt request.
10 - Receive data ready. Read UART RBR to clear interrupt request.
11 - Receive line status. Read UARTx_LSR to clear interrupt request.
Figure 13-13. UART Interrupt Identification Registers
The TX interrupt request is cleared by writing new data to the
register or by reading the
the
UARTx_IIR
want to transmit further data.
If software stops transmission, it must read the
the interrupt request. As long as the
(indicating that another interrupt of higher priority is pending), the
empty latch cannot be cleared by reading
UARTx_THR
ADSP-BF537 Blackfin Processor Hardware Reference
bit signals that an interrupt is pending. The
NINT
9 8 7
0 0 0 0 0 0 0
UARTx_IIR
register read in the case where the service routine does not
UART Port Controllers
empty interrupt has the low-
UARTx_THR
Figure 13-13
6 5 4 3 2 1 0
0 0 0 0 0 0 1
register. Please note the special role of
UARTx_IIR
register reads 0x04 or 0x06
UARTx_IIR
STA-
UARTx_IIR
shows how to
Reset = 0x0001
NINT (Pending interrupt)
0 - Interrupt pending
1 - No interrupt pending
UARTx_THR
register to reset
.
UARTx_IIR
13-29