transaction is initiated by enabling the SPI for DMA receive mode. Subse-
quent individual transactions are initiated by a DMA read of the
. A value of 11 selects DMA transmit mode and the transaction is
SPI_RDBR
initiated by a DMA write of the
The
bit is used to enable the
PSSE
can be disabled, freeing up a chip pin as general-purpose I/O.
SPISS
The
bit enables the
EMISO
environment where the master wishes to transmit to various slaves at one
time (broadcast). Only one slave is allowed to transmit data back to the
master. Except for the slave from whom the master wishes to receive, all
other slaves should have this bit cleared.
The
and
SPE
MSTR
the
register is set. See
SPI_STAT
page
10-21.
Figure 10-12 on page 10-41
Clock Signals
The
signal is a gated clock that is only active during data transfers for
SCK
the duration of the transferred word. The number of active edges is equal
to the number of bits driven on the data lines. The clock rate can be as
high as one-fourth of the
determined by the 16-bit value of
is ignored. When the SPI device is a master,
SPI_BAUD
nal. When the SPI is a slave,
the serial clock if the slave select input is driven inactive (high).
The
signal is used to shift out and shift in the data driven onto the
SCK
and
MISO
MOSI
clock (the active edge) and sampled on the opposite edge of the clock (the
sampling edge). Clock polarity and clock phase relative to data are pro-
grammable into
ADSP-BF537 Blackfin Processor Hardware Reference
SPI_TDBR
pin as an output. This is needed in an
MISO
bits can be modified by hardware when the
"Mode Fault Error (MODF)" on
provides the bit descriptions for
rate. For master devices, the clock rate is
SCLK
SCK
lines. The data is always shifted out on one edge of the
and define the transfer format.
SPI_CTL
SPI Compatible Port Controllers
.
input for master. When not used,
SPISS
. For slave devices, the value in
SPI_BAUD
is an input signal. Slave devices ignore
bit of
MODF
.
SPI_CTL
is an output sig-
SCK
10-19
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