Autobaud Mode - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

Modes of Operation
overflowed and
registers were updated only if a trailing edge was detected at a previous
measurement report.
Software can count the number of error report interrupts between mea-
surement report interrupts to measure input signal periods longer than
0xFFFF FFFF. Each error report interrupt adds a full 2
the total for the period, but the width is ambiguous. For example, in
Figure 15-14 the period is 0x1 0000 0004 but the pulse width could be
either 0x0 0000 0002 or 0x1 0000 0002.
The waveform applied to the
cycle, but the minimum
mum high time is one
TMRx
input frequency is
the mode timer would measure
WDTH_CAP
Pulse Width = 1

Autobaud Mode

In mode, some of the timers can provide autobaud detection for
WDTH_CAP
the Universal Asynchronous Receiver/Transmitter (UART) and Control-
ler Area Network (CAN) interfaces. The timer input select (
in the
TIMERx_CONFIG
instead of the
TMRx
tion can be used for initial bit rate negotiations as well as for detection of
bit rate drifts while the interface is operation. For details with the UART
interface, see Chapter 13, "UART Port
CAN interface, see
External Event (EXT_CLK) Mode
Use the
EXT_CLK
count external events, that is, signal edges on the
input in this mode.
15-34
, the
PERIOD_CNT = 0
TMRx
low time is one
TMRx
period. This implies the maximum
SCLK
with a 50% duty cycle. Under these conditions,
SCLK/2
.
register causes the timer to sample the
pin when enabled for
Chapter 9, "CAN
mode, sometimes referred to as the "counter mode," to
Figure 15-16 shows a flow diagram for
ADSP-BF537 Blackfin Processor Hardware Reference
and
TIMERx_PERIOD
pin is not required to have a 50% duty
period and the mini-
SCLK
Period = 2
mode. Autobaud detec-
WDTH_CAP
Controllers". For details with the
Module".
TMRx
TIMERx_WIDTH
32
counts to
SCLK
TMRx
and
) bit
TIN_SEL
pin
TACIx
pin which is an
mode.
EXT_CLK