Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1042

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Specific Blackfin Boot Modes

Figure 19-32. TWI Slave Boot Mode

On the Blackfin processor, in both TWI master and slave boot

modes, the upper 256 bytes of data bank A starting at address

0xFF90 3F00 must not be used. The boot ROM code uses this

space for the TWI boot modes to temporarily hold the serial data

which is then transferred to L1 instruction memory using DMA.

UART Slave Mode Boot via Master Host

(BMODE = 111)

UART booting on the Blackfin processor is supported only through

UART0, and the Blackfin processor is always a slave.

Using an autobaud detection sequence, a boot-stream-formatted program

is downloaded by the host. The host agent selects a bit rate within the

UART's clocking capabilities. When performing the autobaud, the UART

expects an "@" character (0x40, eight bits data, one start bit, one stop bit,

no parity bit) on the UART0

hardware support and the mathematical operations to perform for this

autobaud detection is explained in

Chapter 15, "General-Purpose

an acknowledgement, and the host can then download the boot stream.

The acknowledgement consists of the following four bytes:

(SLAVE DEVICE)

input to determine the bit rate. The

Timers". The boot kernel then replies with

. The host is requested to not send further

ADSP-BF537 Blackfin Processor Hardware Reference

I 2 C-COMPATIBLE HOST

(MASTER DEVICE)

"Autobaud Mode" on page 15-34