Interrupt Output - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

into the shift register and transmitted. In this case, the data in
may not match what was transmitted. This error can easily be avoided by
proper software control. The

Interrupt Output

The SPI has two interrupt output signals: a data interrupt and an error
interrupt.
The behavior of the SPI data interrupt signal depends on the
in the
SPI_CTL
acts as a DMA request and is generated when the DMA FIFO is ready to
be written to (
mode (
TIMOD = 0X
ready to be written to (
read from (
TIMOD = 00
An SPI error interrupt is generated in a master when a mode fault error
occurs, in both DMA and non-DMA modes. An error interrupt can also
be generated in DMA mode when there is an underflow (
) or an overflow (
TIMOD = 11
non-DMA mode, the underflow and overflow conditions set the
bits in the
RBSY
error interrupt.
For more information about this interrupt output, see the discussion of
the bits in
TIMOD
Functional Description
The following sections describe the functional operation of the SPI.
ADSP-BF537 Blackfin Processor Hardware Reference
TXCOL
register. In DMA mode (
) or read from (
TIMOD = 11
), a data interrupt is generated when the
TIMOD = 01
).
RBSY
register, respectively, but do not generate an
SPI_STAT
"SPI Control" on page
SPI Compatible Port Controllers
bit is sticky (W1C).
), the data interrupt
TIMOD = 1X
TIMOD = 10
) or when the
SPI_RDBR
when ) error condition. In
TIMOD = 10
10-18.
SPI_TDBR
field
TIMOD
). In non-DMA
is
SPI_TDBR
is ready to be
when
TXE
and
TXE
10-23