Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1150

Length registers.
A Data Address Generator (DAG) register that specifies the range of
addresses in a circular buffer.
Level 1 (L1) memory.
Memory that is directly accessed by the core with no intervening memory
subsystems between it and the core.
Level 2 (L2) memory.
Memory that is at least one level removed from the core. L2 memory has a
larger capacity than L1 memory, but it requires additional latency to
access.
level-sensitive interrupts.
A signal or interrupt that the processor detects if the input signal is low
(active) when sampled on the rising edge of .
CLKIN
LIFO (Last In, First Out).
A data structure from which the next item taken out is the most recent
item put in.
little endian.
The native data store format of the processor. Words and half words are
stored in memory (and registers) with the least significant byte at the low-
est byte address and the most significant byte at the highest byte address of
the data storage location.
loop.
A sequence of instructions that executes several times.
LRU.
See Least Recently Used algorithm
G-14 ADSP-BF537 Blackfin Processor Hardware Reference