Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1195

PLL
enabled, 20-13
enabled but bypassed,
full on mode, effect of programming for,
20-16
and internal clocks, 2-4
maximum performance mode,
modification, activating changes to DF
or MSEL, 20-15
modification in active mode,
multiplier select (MSEL) field,
new multiplier ratio,
operating modes, operational
characteristics, 20-8
operating mode transitions,
PDWN bit, 20-11
PLL_LOCKED bit,
PLL_OFF bit, 20-13
PLL status (table), 20-8
power domains, 20-18
powering down core,
power savings by operating mode (table),
20-8
processing during PLL programming
sequence, 20-16
programming sequence,
registers, table, 20-25
relocking after changes,
removing power to the PLL,
RTC interrupt, 20-10,
SCLK derivation, 20-2,
sleep mode, 20-9, 20-16
STOPCK bit, 20-11
voltage control, 20-7,
wakeup signal, 20-16
PLL control register (PLL_CTL), 20-25,
20-26
PLL_CTL (PLL control register), 20-4,
20-25, 20-26
ADSP-BF537 Blackfin Processor Hardware Reference
(continued)
20-9
20-9
20-13
20-3
20-13
20-14
20-16
20-22
20-15
20-16
20-13
20-17
20-3
20-21
PLL divide register (PLL_DIV),
PLL_DIV (PLL divide register), 20-5,
20-25
PLL_LOCKCNT (PLL lock count
register), 20-25, 20-27
PLL lock count register
(PLL_LOCKCNT),
PLL_LOCKED bit, 20-26
PLL_OFF bit, 20-26
PLL_STAT (PLL status register), 20-25,
20-26
PLL status register (PLL_STAT),
PLL VCO frequency, changing,
PMAP[3:0] field, 5-7, 5-48, 5-49,
polarity, GPIO, 14-14
POLC bit, 7-5, 7-26, 7-27
polling DMA registers,
POLS bit, 7-5, 7-26, 7-27
PORT_CFG[1:0] field, 7-5, 7-27,
port connection, SPORT,
PORT_DIR bit, 7-5, 7-27,
PORT_EN bit, 7-27, 7-30
port F
and general-purpose timers,
GPIO, 14-5, 14-10
interrupt A channel,
multiplexing, 14-5
peripherals, 14-2
and PPI, 7-3, 14-4
and SPI, 10-4
structure, 14-4
timer port setup, 15-52
timers, 14-4
UART, 14-4
PORTF_FER and booting,
PORTF_FER (function enable register),
5-6, 7-4, 14-9
Index
20-25
20-27
20-26
6-45
5-71
5-56
7-30
12-7
7-30
15-4
14-19
19-20
I-33