Core Timer Registers - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

Core Timer Registers

Core Timer Registers
Core timer registers (0xFFE0 3000 – 0xFFE0 300C) are listed in
Table A-23.
Table A-23. Core Timer Registers
Memory-mapped
Address
0xFFE0 3000
0xFFE0 3004
0xFFE0 3008
0xFFE0 300C
Processor-Specific Memory Registers
Processor-specific memory registers (0xFFE0 0004 – 0xFFE0 0300) are
listed in Table
Table A-24. Processor-Specific Memory Registers
Memory-mapped
Address
0xFFE0 0004
0xFFE0 0300
A-36
Register Name
TCNTL
TPERIOD
TSCALE
TCOUNT
A-24.
Register Name
DMEM_CONTROL
DTEST_COMMAND
ADSP-BF537 Blackfin Processor Hardware Reference
See Page
"Core Timer Control Register" on page 16-4
"Core Timer Period Register" on page 16-6
"Core Timer Scale Register" on page 16-7
"Core Timer Count Register" on page 16-5
See Page
"L1 Data Memory Control Register" on
page 3-9
"Data Test Command Register" on page 3-10