Handshake Mdma Control Registers - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

Handshake MDMA Control Registers

Table A-21. Ethernet MAC Registers (Cont'd)
Memory-mapped
Address
0xFFC0 31C8
0xFFC0 31CC
0xFFC0 31D0
0xFFC0 31D4
0xFFC0 31D8
Handshake MDMA Control Registers
HMDMA registers (0xFFC0 3300 – 0xFFC0 33FF) are listed in
Table A-22.
Table A-22. HMDMA Registers
Memory-mapped
Address
0xFFC0 3300
0xFFC0 3304
0xFFC0 3308
0xFFC0 330C
0xFFC0 3310
A-34
Register Name
EMAC_TXC_LT254
EMAC_TXC_LT512
EMAC_TXC_LT1024
EMAC_TXC_GE1024
EMAC_TXC_ABORT
Register Name
HMDMA0_CONTROL
HMDMA0_ECINIT
HMDMA0_BCINIT
HMDMA0_
ECURGENT
HMDMA0_
ECOVERFLOW
ADSP-BF537 Blackfin Processor Hardware Reference
See Page
"MAC Management Counter Registers" on
page 8-54
"MAC Management Counter Registers" on
page 8-54
"MAC Management Counter Registers" on
page 8-54
"MAC Management Counter Registers" on
page 8-54
"MAC Management Counter Registers" on
page 8-54
See Page
"Handshake MDMA Control Registers" on
page 5-100
"Handshake MDMA Initial Edge Count Regis-
ters" on page 5-103
"Handshake MDMA Initial Block Count Reg-
isters" on page 5-101
"Handshake MDMA Edge Count Urgent Reg-
isters" on page 5-104
"Handshake MDMA Edge Count Overflow
Interrupt Registers" on page 5-104