Pll Programming Sequence Continues - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

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When the wakeup signal has been asserted, the instruction
sequence continues with the
Programming Sequence" on page
transition to:
—Active mode if
—Full on mode if the
• If the
PLL_CTL
mode, the processor immediately transitions to deep sleep mode
and waits for an RTC interrupt or hardware reset signal:
—An RTC interrupt causes the processor to enter active
operating mode and continue with the
the sequence, as described below.
—A hardware reset causes the processor to execute the reset
sequence. For more information about hardware reset, see
the ADSP-BF53x/BF56x Blackfin Processor Programming
Reference.
• If no operating mode transition is programmed, the PLL generates
a wakeup signal, and the processor continues with the
tion in the sequence, as described in the following section.

PLL Programming Sequence Continues

The instruction sequence shown in
continues with the
restored, and normal program flow resumes.
To prevent spurious activity, DMA should be suspended while exe-
cuting this instruction sequence.
ADSP-BF537 Blackfin Processor Hardware Reference
Dynamic Power Management
STI
BYPASS
BYPASS
register is programmed to enter deep sleep operating
Listing 20-1
instruction. Interrupts are re-enabled,
STI
instruction, as described in
20-15, causing the processor to
in the
register is set
PLL_CTL
bit is cleared
instruction in
STI
and
Listing 20-2
"PLL
instruc-
STI
then
is
IMASK
20-17

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