Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1029

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0x000000 until a valid 8-, 16-, or 24-bit addressable EEPROM is

detected. It then begins clocking data into the beginning of L1 instruction

For SPI master mode booting, the processor is configured as an SPI master

connected to an SPI memory.

tions needed for this mode.

ADSP-BF534/BF536/BF537

(MASTER SPI DEVICE)

Figure 19-17. Blackfin - SPI Memory Pin-to-Pin Connections

A pull-up resistor on

properly. For this reason, the Blackfin processor reads a 0xFF on

written on the

kernel to automatically determine the type of SPI memory con-

nected prior to the boot procedure.

Although the pull-up resistor on the

pull-up resistors might also be worthwhile as well—pull up the chip select

fin processor is in reset. Also, experience has shown that a pull-down

resistor on the

debugging the boot process.

ADSP-BF537 Blackfin Processor Hardware Reference

Figure 19-17

pin if the SPI memory is not responding (that is, no data

pin by the SPI memory). This enables the boot

to ensure the SPI memory is not activated while the Black-

line results in nicer plots on the oscilloscope in case of

System Reset and Booting

shows the pin-to-pin connec-

(SLAVE SPI DEVICE)

is required for this boot mode to work

line is mandatory, additional