Sport0 Controller Registers - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

SPORT0 Controller Registers

SPORT0 Controller Registers
SPORT0 controller registers (0xFFC0 0800 – 0xFFC0 08FF) are listed in
Table A-9.
Table A-9. SPORT0 Controller Registers
Memory-mapped
Address
0xFFC0 0800
0xFFC0 0804
0xFFC0 0808
0xFFC0 080C
0xFFC0 0810
0xFFC0 0818
0xFFC0 0820
0xFFC0 0824
0xFFC0 0828
0xFFC0 082C
0xFFC0 0830
0xFFC0 0834
A-12
Register Name
SPORT0_TCR1
SPORT0_TCR2
SPORT0_TCLKDIV
SPORT0_TFSDIV
SPORT0_TX
SPORT0_RX
SPORT0_RCR1
SPORT0_RCR2
SPORT0_RCLKDIV
SPORT0_RFSDIV
SPORT0_STAT
SPORT0_CHNL
ADSP-BF537 Blackfin Processor Hardware Reference
See Page
"SPORTx Transmit Configuration 1 Register"
on page 12-48
"SPORTx Transmit Configuration 2 Register"
on page 12-49
"SPORTx Transmit Serial Clock Divider Reg-
ister" on page 12-64
"SPORTx Transmit Frame Sync Divider Reg-
ister" on page 12-65
"SPORTx Transmit Data Register" on
page 12-60
"SPORTx Receive Data Register" on
page 12-62
"SPORTx Receive Configuration 1 Register"
on page 12-54
"SPORTx Receive Configuration 2 Register"
on page 12-55
"SPORTx Receive Serial Clock Divider Regis-
ter" on page 12-65
"SPORTx Receive Frame Sync Divider Regis-
ter" on page 12-66
"SPORTx Status Register" on page 12-64
"SPORTx Current Channel Register" on
page 12-68