Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 851

The GPIO direction registers are read-write registers with each bit posi-
tion corresponding to a particular GPIO. A logic 1 configures a GPIO as
an output, driving the state contained in the GPIO data register if the
peripheral function is not enabled by the function enable registers. A logic
0 configures a GPIO as an input.
Note when using the GPIO as an input, the corresponding bit
should also be set in the GPIO input enable register. Otherwise,
changes at the input pins will not be recognized by the processor.
The GPIO input enable registers (
) are used to enable the input buffers on any GPIO that is
PORTHIO_INEN
being used as an input. Leaving the input buffer disabled eliminates the
need for pull-ups and pull-downs when a particular
not used in the system. By default, the input buffers are disabled.
Once the input driver of a GPIO pin is enabled, the GPIO is not
allowed to operate as an output anymore. Never enable the input
driver (by setting
ting
PORTxIO_DIR
A write operation to any of the GPIO data registers sets the value of all
GPIOs in this port that are configured as outputs. GPIOs configured as
inputs ignore the written value. A read operation returns the state of the
GPIOs defined as outputs and the sense of the inputs, based on the polar-
ity and sensitivity settings, if their input buffers are enabled.
helps to interpret read values in GPIO mode, based on the settings of the
PORTxIO_POLAR
ADSP-BF537 Blackfin Processor Hardware Reference
PORTxIO_INEN
bits) for the same GPIO.
, , and
PORTxIO_EDGE
General-Purpose Ports
,
PORTFIO_INEN PORTGIO_INEN
PFx
bits) and the output driver (by set-
registers.
PORTxIO_BOTH
, and
, , or pin is
PGx PHx
Table 14-2
14-11