Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1190

Index
MCDTXPE bit, 12-67
MCMEN bit, 12-18, 12-67
MCOMP bit, 11-18, 11-43
MCOMPM bit, 11-41,
MCx bit, 9-69
MDCDIV[5:0] field, 8-93,
MDIO station management interface,
MDIR bit, 11-34, 11-36
MDMA controllers, 5-9
MDMA_ROUND_ROBIN_COUNT[4:
0] field, 5-52, 5-106
MDMA_ROUND_ROBIN_PERIOD
field, 5-52, 5-106
MDMA_yy_CONFIG (DMA
configuration registers),
MDMA_yy_CURR_ADDR (current
address registers),
MDMA_yy_CURR_DESC_PTR (current
descriptor pointer registers),
MDMA_yy_CURR_X_COUNT (current
inner loop count registers), 5-86,
MDMA_yy_CURR_Y_COUNT (current
outer loop count registers),
MDMA_yy_IRQ_STATUS (interrupt
status registers), 5-78,
MDMA_yy_NEXT_DESC_PTR (next
descriptor pointer registers),
MDMA_yy_PERIPHERAL_MAP
(peripheral map registers),
MDMA_yy_START_ADDR (start
address registers),
MDMA_yy_X_COUNT (inner loop
count registers), 5-85
MDMA_yy_X_MODIFY (inner loop
address increment registers),
MDMA_yy_Y_COUNT (outer loop
count registers), 5-90
MDMA_yy_Y_MODIFY (outer loop
address increment registers),
MDn bit, 9-70
I-28
11-42
8-94
8-7
5-74
5-83
5-96
5-87
5-91
5-79
5-94
5-71
5-82
5-88
5-93
ADSP-BF537 Blackfin Processor Hardware Reference
measurement report, general-purpose
timers, 15-28, 15-29,
memory, 3-1 to 3-10
accesses to internal, 3-2
ADSP-BF534, 3-3
ADSP-BF536, 3-4
ADSP-BF537, 3-5
architecture, 1-4, 3-1
asynchronous, 3-2
asynchronous interface,
asynchronous region,
boot ROM, 3-8
configurations, 1-5, 3-1,
external, 1-6, 3-8
external memory, 6-6
external memory map,
external SDRAM, 6-27
internal, 1-6
internal bank, 6-33,
I/O space, 1-7
L1, 2-4
L1 data, 1-6, 3-7
L1 data cache, 3-8
L1 instruction, 1-6,
L1 scratchpad, 1-6
moving data between SPORT and,
12-38
off-chip, 1-6
on-chip, 1-6
SDRAM, 3-2
start locations of L1 instruction memory
subbanks, 3-6
structure, 1-4
unpopulated, 6-10
memory conflict, DMA,
memory DMA, 1-8, 5-9
bandwidth, 5-47
buffers, 5-10
channels, 5-9
descriptor structures,
15-30
21-5
6-2
3-2
3-2
G-12
3-5
5-53
5-67