Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1139

Glossary
cache block.
The smallest unit of memory that is transferred to/from the next level of
memory from/to a cache as a result of a cache miss.
cache hit.
A memory access that is satisfied by a valid, present entry in the cache.
cache line.
Same as cache block. In this document, cache line is used for cache block.
cache miss.
A memory access that does not match any valid entry in the cache.
cache tag.
Upper address bits, stored along with the cached data line, to identify the
specific address source in memory that the cached line represents.
Cacheability Protection Lookaside Buffer (CPLB).
Storage area that describes the access characteristics of the core memory
map.
CAM (Content Addressable Memory).
Also called associative memory. A memory device that includes compari-
son logic with each bit of storage. A data value is broadcast to all words in
memory; it is compared with the stored values; and values that match are
flagged.
CAS (Column Address Strobe).
A signal sent from the SDC to a DRAM device to indicate that the col-
umn address lines are valid.
ADSP-BF537 Blackfin Processor Hardware Reference G-3