Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1214

Index
UART
clock, 13-12
clock rate, 2-4
code examples, 13-32
data words, 13-4
divisor reset, 13-30
DMA channels, 13-17
DMA mode, 13-17
errors during reception,
external interfaces, 13-2
features, 13-1
glitch filtering, 13-9
initialization, 13-32
internal interfaces, 13-3
interrupt channels, 13-27
interrupt conditions,
interrupts, 13-10
IrDA mode, 13-2
IrDA receiver, 13-9
IrDA receiver pulse detection,
IrDA transmit pulse,
IrDA transmitter, 13-8
and ISRs, 13-16
loopback mode, 13-23
mixing modes, 13-18
modem status, 13-2
non-DMA interrupt operation,
non-DMA mode, 13-15
pins, 14-2
polling, 13-37
port F, 14-4
receive operation, 13-6
receive sampling window,
registers, table, 13-20
sampling clock period,
slave boot mode, 19-56
standard, 13-1
string transmission, 13-36
switching from DMA to non-DMA,
13-18
I-52
(continued)
13-7
13-28
13-10
13-8
13-38
13-9
13-8
ADSP-BF537 Blackfin Processor Hardware Reference
UART
switching from non-DMA to DMA,
13-19
and system DMA, 13-27
timers, 13-4
transmission, 13-5
transmission SYNC bit use,
UART divisor latch high byte registers
(UARTx_DLH),
UART divisor latch low byte registers
(UARTx_DLL), 13-30
UART global control registers
(UARTx_GCTL),
UART interrupt enable registers
(UARTx_IER), 13-27,
UART interrupt identification registers
(UARTx_IIR), 13-12,
UART line control registers
(UARTx_LCR), 13-21
UART line status registers (UARTx_LSR),
13-24
UART modem control registers
(UARTx_MCR),
UART receive buffer registers
(UARTx_RBR), 13-6,
UART scratch registers (UARTx_SCR),
13-31
UART transmit holding registers
(UARTx_THR),
UARTx_DLH (UART divisor latch high
byte registers), 13-20,
UARTx_DLL (UART divisor latch low
byte registers), 13-20,
UARTx_GCTL (UART global control
registers), 13-20, 13-31
UARTx_IER (UART interrupt enable
registers), 13-20, 13-27,
UARTx_IIR (UART interrupt
identification registers), 13-12, 13-20,
13-29
(continued)
13-39
13-30
13-31
13-28
13-29
13-23
13-26
13-26
13-30
13-30
13-28