Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 689

Two Wire Interface Controller
WRITE TO TWI_CONTROL TO SET
PRESCALE AND ENABLE THE TWI
WRITE TO TWI_CLK_DIV
WRITE TO TWI_MASTER_ADDR WITH THE
ADDRESS OF THE TARGETED DEVICE
WRITE TO TWI_FIFO_CTL TO SELECT WHETHER
1 OR 2 BYTES GENERATE INTERRUPTS
WRITE TO TWI_INT_MASK TO UNMASK
TWI EVENTS TO GENERATE INTERRUPTS
WRITE TO TWI_SLAVE_CTL TO
ENABLE SLAVE FUNCTIONALITY
WRITE TWI_MASTER_CTL WITH COUNT, WRITE TWI_MASTER_CTL WITH COUNT,
TRANSMIT
RECEIVE
TRANSFER
MDIR SET, AND MEN SET. THIS MDIR CLEARED, AND MEN SET. THIS
DIRECTION
STARTS THE TRANSFER STARTS THE TRANSFER
WAIT FOR INTERRUPTS WAIT FOR INTERRUPTS
MCOMP XMTSERV
MCOMP
RCVSERV
INTERRUPT
INTERRUPT
WRITE TWI_INT_STAT
SOURCE
SOURCE
TO CLEAR INTERRUPT
MERR
MERR
WRITE DATA INTO
READ DATA FROM
TWI_XMT_DATA
TWI_RCV_DATA
REGISTER
DONE
REGISTER
WRITE TWI_INT_STAT
WRITE TWI_INT_STAT
TO CLEAR INTERRUPT
READ TWI_MASTER_STAT TO GET ERROR CAUSE
TO CLEAR INTERRUPT
HANDLE ERROR AS APPROPRIATE AND W1C THE
CORRESPONDING BIT IN TWI_MASTER_STAT
WRITE TWI_INT_STAT TO CLEAR MERR BIT
WAIT FOR INTERRUPTS
Figure 11-10. TWI Master Mode
ADSP-BF537 Blackfin Processor Hardware Reference 11-29