Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 814

Programming Model
The flag is set when
THRE
when the processor loads new data into
when it is not empty overwrites the register with the new value and the
previous character is never transmitted.
The flag signals when new data is available in
DR
cleared automatically when the processor reads from
when it is not full returns the previously received value. When
UARTx_RBR
is not read in time, newly received data overwrites
UARTx_RBR
and the flag is set.
OE
With interrupts disabled, these status flags can be polled to determine
when data is ready to move. Note that because polling is processor inten-
sive, it is not typically used in real-time signal processing environments.
Be careful if transmit and receive are served by different software threads,
because read operations on
tive. Polling the
is an alternate method of operation to consider. Software can
SIC_MASK
write up to two words into the
UART clock. As soon as the
Alternatively, UART writes and reads can be accomplished by interrupt
service routines (ISRs). Separate interrupt lines are provided for UART
TX, UART RX, and UART error. The independent interrupts can be
enabled individually by the
The ISRs can evaluate the status bit field within the
determine the signalling interrupt source. If more than one source is sig-
nalling, the status field displays the one with the highest priority.
Interrupts also must be assigned and unmasked by the processor's inter-
rupt controller. The ISRs must clear the interrupt latches explicitly. See
Figure 13-13 on page
13-16
UARTx_THR
UART_LSR
register without enabling the interrupts by
SIC_ISR
UARTx_THR
bit is set, those two words are sent.
UCEN
UARTx_IER
13-29.
ADSP-BF537 Blackfin Processor Hardware Reference
is ready for new data and cleared
. Writing
UARTx_THR
UARTx_RBR
UARTx_RBR
and registers are destruc-
UART_IIR
register before enabling the
register.
UARTx_IIR
UARTx_THR
. This flag is
. Reading
UARTx_RBR
register to