Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1187

L
L1 data cache, 3-8
L1 data memory, 1-6
subbanks, 3-7
L1 instruction memory, 1-6,
address alignment, 3-5
subbanks, 3-6
L1 memory, 2-4
and DMA, 5-6
L1 scratchpad RAM, 1-6
LARFS bit, 12-35, 12-54,
large descriptor mode, DMA,
large model mode, DMA,
LateCollisions register,
late frame sync, 12-18,
latency
DAB, 2-10
DMA, 5-27
general-purpose ports,
powerup, 6-56
SDC, 6-41
SDRAM, 6-73
LATFS bit, 12-35, 12-48,
LB bit, 8-64, 8-65
LCRTE bit, 8-28
LCTRE bit, 8-64, 8-66
LdrViewer, 19-59
lines per frame register (PPI_FRAME),
7-35, 7-36
line terminations, SPORT,
linked list, DMA, 8-127
little endian byte order,
loader file, 19-11
loader utility, 19-11
LOCKCNT[15:0] field,
locked transfers, DMA,
loopback feature, PPI,
loopback mode, UART,
LOOP bit, 13-23
LOSTARB bit, 11-14,
ADSP-BF537 Blackfin Processor Hardware Reference
3-5
12-57
5-17
5-76
8-61
12-35
14-9
12-52
12-9
11-44
20-27
2-10
7-11
13-23
11-38
LRFS bit, 12-31, 12-33, 12-54,
LSBF bit, 10-41
LT_ERR_OVR bit, 7-31,
LT_ERR_OVR flag, 7-32
LT_ERR_UNDR bit, 7-31,
LT_ERR_UNDR flag,
LTFS bit, 12-20, 12-31, 12-33, 12-48,
12-52
M
MAA bit, 9-45
MAC, 1-14, 8-1 to 8-132
aborted frames, 8-16
address filter evaluation,
address setup, 8-129
alternative descriptor structure,
block diagram, 8-3
clocking, 8-4
code examples, 8-126
configuration, 8-46
configuring address registers,
configuring interrupts,
configuring PHY, 8-50
continuous polling, 8-44
control frames, 8-16
CRC-16 hash value calculation,
CRC-32 address calculation,
CRC state, 8-37
descriptor structure, alternative,
discarded frames, 8-16
DMA configuration,
DMA data transfer, 8-50
DMA descriptor pairs, 8-12,
DMA descriptors, 8-127
ethernet event interrupts, 8-38,
Ethernet frame buffer,
Ethernet frame header,
flexible descriptor structure,
frame filter evaluation,
Index
12-57
7-33
7-33
7-32
8-14
8-26
8-48
8-47
8-38
8-73
8-26
8-126
8-24
8-39
8-128
8-50
8-27
8-15
I-25