Table of Contents
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Index
PF0 bit,
5-6
PF0 pin,
14-13
PF1 bit,
5-6
PFDE bit, 5-6,
14-22
PFFE bit,
14-22
PFLAG[3:0] field,
19-14
-PFLAG switch,
19-19
PFS4E bit,
14-22
PFS5E bit,
14-22
PFS6E bit,
14-22
PFTE bit,
14-22
PFx pin,
10-8
PGRE bit,
14-22
PGSE bit,
14-22
PGTE bit,
14-22
PHY,
8-4
configuring,
8-50
control routines,
8-130
initialization, minimum requirements,
8-132
read access,
8-131
PHYAD[4:0] field,
8-76
PHYCLKOE bit,
8-47
PHYIE bit, 8-93,
8-94
PHYINT bit, 8-95,
8-97
PHYINT interrupt,
8-40
PHYWE bit,
20-27
pins,
21-1
MAC,
8-5
multiplexing,
14-1
PPI,
7-4
unused,
21-12
pin state during SDC commands (table),
6-48
pin terminations, SPORT,
pipeline, lengths of,
5-57
pipelining
DMA requests,
5-41
SDC supported,
6-75
I-32
12-9
ADSP-BF537 Blackfin Processor Hardware Reference
PJCE[1:0] field,
14-22
PJSE bit,
14-22
PJx pin,
10-8
PLL,
20-1
to
20-34
active mode,
20-9
active mode, effect of programming for,
20-16
applying power to the PLL,
block diagram,
20-3
BYPASS bit, 20-9,
20-17
bypassing onboard regulation,
CCLK derivation,
20-3
changing CLKIN-to-VCO multiplier,
20-13
changing clock ratio,
clock dividers,
20-3
clocking to SDRAM,
clock multiplier ratios,
code example, active mode to full on
mode,
20-29
code example, changing clock multiplier,
20-31
code example, changing internal voltage
levels,
20-33
code example, full on mode to active
mode,
20-30
code example, setting wakeups and
entering hibernate state,
code examples,
20-28
configuration,
20-3
control bits,
20-11
deep sleep mode, effect of programming
for,
20-17
design,
20-2
disabled,
20-13
divide frequency,
20-3
DMA access, 20-9,
20-17
dynamic power management controller
(DPMC),
20-7
20-13
20-20
20-6
20-10
20-3
20-32
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