Global Interrupt - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

Functional Operation

Global Interrupt

The global interrupt logic is implemented with three registers—the global
interrupt mask register (
enabled or disabled separately; the global interrupt status register
( ); and the global interrupt flag register (
CAN_GIS
mask bits only affect the content of the global interrupt flag register
( ). If the mask bit is not set, the corresponding flag bit is not set
CAN_GIF
when the event occurs. The interrupt status bits in the global interrupt
status register, however, are always set if the corresponding interrupt event
occurs, independent of the mask bits. Thus, the interrupt status bits can
be used for polling of interrupt events.
The global interrupt output (
ter is only asserted if a bit in the
remains set as long as at least one bit in the interrupt flag register
is set. All bits in the interrupt status and in the interrupt flag registers
remain set until cleared by software or a software reset has occurred.
There are several interrupt events that can activate this
• Access denied interrupt (
At least one access to the mailbox RAM occurred during a data
update by internal logic.
• External trigger output interrupt (
The external trigger event occurred.
• Universal counter exceeded interrupt (
There was an overflow of the universal counter (in time stamp
mode or event counter mode) or the counter has reached the value
0x0000 (in watchdog mode).
9-24
), where each interrupt source can be
CAN_GIM
) bit in the global interrupt status regis-
GIRQ
CAN_GIF
,
ADIM
ADSP-BF537 Blackfin Processor Hardware Reference
CAN_GIF
register is set. The
GIRQ
, )
ADIS ADIF
, ,
EXTIM EXTIS EXTIF
,
UCEIM UCEIS
). The interrupt
bit
GIRQ
CAN_GIF
interrupt:
)
, )
UCEIF