Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1203

SDC commands, 6-47
SDCI bit, 6-78
SDEASE bit, 6-78, 6-79
SDIR bit, 11-15, 11-33
SDPUA bit, 6-78, 6-79
SDQM[1:0] encodings during writes,
SDRAM, 1-6
address connections,
address mapping, 6-27
auto-refresh command, 6-35,
bank activate command,
banks, 3-8
bank size, 6-2
burst length, 6-33
burst type, 6-34
and busmastership, 6-8
CAS latency, 6-34
clock enables, setting,
column read/write, 6-32
commands, 6-34
configuration, 6-25
ERMS command, 6-34
external bank, 6-33
external memory, 6-27
interface signals, 6-30
internal banks, 6-29
internal memory banks,
latency, 6-73
memory banks, 6-3
memory size, 6-33
memory space, 6-2
MRS command, 6-34
multibank operation,
no operation command,
operation parameters, initializing,
parallel connection, 6-29
performance, 6-31
power-up sequence,
powerup sequence, 6-73
precharge all command,
ADSP-BF537 Blackfin Processor Hardware Reference
6-52
6-42
6-52
6-35
6-67
6-33
6-43
6-54
6-49
6-45
6-35
SDRAM
precharge command,
read command, 6-35
read transfers, 6-52
read/write command,
refresh, 6-32
reserved, 6-2
row activation, 6-32
row precharge, 6-33
self-refresh mode, 6-35, 6-36,
shared, 6-46
sharing external, 6-72
size configuration, 6-62
sizes supported, 3-8,
smaller than 16M byte,
specification of system,
stall cycles, 6-32
start address, 6-2
system block diagram, 6-58,
timing specs, 6-36
write command, 6-35
SDRAM controller, See SDC
SDRAM control status register
(EBIU_SDSTAT),
SDRAM memory, 3-2
SDRAM memory bank control register
(EBIU_SDBCTL), 6-62,
SDRAM memory global control register
(EBIU_SDGCTL), 6-67,
SDRAM refresh rate control register
(EBIU_SDRRC),
SDRS bit, 6-56, 6-78,
SDSRA bit, 6-78
seconds (1 Hz) event flag bit,
seconds (1Hz) interrupt enable bit,
seconds[5:0] field, 18-20,
self-refresh command,
self-refresh mode, 6-35, 6-36, 6-53,
entering, 6-53
exiting, 6-54
Index
(continued)
6-35
6-51
6-53
6-25
6-65
6-29
6-59
6-78
6-63
6-68
6-60
6-79
18-21
18-20
18-22
6-53
6-81
I-41