Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1154

PF (Programmable Flag).
General-purpose I/O pins. Each PF pin can be individually configured as
either an input or an output pin, and each PF pin can be further config-
ured to generate an interrupt.
Phase Locked Loop (PLL).
An on-chip frequency synthesizer that produces a full speed master clock
from a lower frequency input clock signal.
PLL.
See Phase Locked Loop
PPI.
See Parallel Peripheral Interface
precision.
The number of bits after the binary point in the storage format for the
number.
post-modify addressing.
The process in which the Data Address Generator (DAG) provides an
address during a data move and auto-increments after the instruction is
executed.
precharge command.
The precharge command closes a specific active page in an internal bank
and the precharge all command closes all 4 active pages in all 4 banks.
pre-modify addressing.
The process in which the Data Address Generator (DAG) provides an
address during a data move and auto-increments before the instruction is
executed.
G-18 ADSP-BF537 Blackfin Processor Hardware Reference