Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1170

Index
CDPRIO bit, 6-19, 6-21,
channels
defined, serial, 12-23
serial port TDM, 12-23
serial select offset, 12-23
CHNL[9:0] field, 12-67,
CIF, 7-9
circuit board testing, B-1,
circular addressing, 5-61
CKELOW bit, 20-27
CL, 6-37
CL[1:0] field, 6-68, 6-69
clearing interrupt requests,
clear Pxn bit, 14-25
clear Pxn interrupt A enable bit,
clear Pxn interrupt B enable bit,
CLKBUFOE bit, 20-27,
CLKBUF pin, 8-4, 8-47
CLKHI[7:0] field, 11-30
CLKIN, 1-22, 20-1
CLKIN (input clock), 2-4,
CLKIN to VCO, changing the multiplier,
20-16
CLKIN to VCO, changing the multiplier,
example, 20-31
CLKLOW[7:0] field, 11-30
CLKOUT pin, 6-7, 6-69
disabling, 6-74
CLK_SEL bit, 15-13, 15-22, 15-44,
clock
clock signals, 1-22
EBIU, 6-2
frequency for SPORT,
internal, 2-4
MAC, 8-4
managing, 21-1
RTC, 18-4
source for general-purpose timers,
SPI clock signal, 10-4
types, 21-1
I-8
6-44
12-68
B-5
4-23
14-31
14-32
20-28
20-3
15-51
12-64
15-5
ADSP-BF537 Blackfin Processor Hardware Reference
clock divide modulus register,
clock domain synchronization, PPI,
clock input (CLKIN) pin,
clock phase, SPI, 10-14,
clock polarity, SPI, 10-14
clock rate
core timer, 16-1
SPORT, 12-2
clock ratio, changing, 20-6
codecs, connecting to,
column address, 6-64
strobe latency, 6-34,
column read/write, SDRAM,
command inhibit command,
commands
auto-refresh, 6-35, 6-52,
bank activate, 6-35,
bank activation, 6-51
command inhibit, 6-54
DMA control, 5-34,
EMRS, 6-50
ERMS, 6-34
MRS, 6-34, 6-49
no operation, 6-54
precharge, 6-35, G-18
precharge all, 6-35, 6-52
read, 6-35
read/write, 6-51
SDC, 6-47
self-refresh, 6-53
single precharge, 6-52
transfer initiate, 10-24,
write, 6-35
write with data mask,
companding, 12-16, 12-24
defined, 12-29
lengths supported, 12-29
multichannel operations,
12-64
7-16
21-1
10-15
12-1
G-4
6-32
6-54
6-60
G-1
5-35
10-25
6-51
12-24