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PLL_LOCKCNT Register
PLL Lock Count Register (PLL_LOCKCNT)
15 14 13 12 11 10
0xFFC0 0010
0
Figure 20-7. PLL Lock Count Register
VR_CTL Register
Voltage Regulator Control Register (VR_CTL)
15 14 13 12 11 10
0xFFC0 0008
0
CKELOW (Drive
CKE Low During
Reset)
0 - Allow CKE to go
high (=1) during reset
1 - Maintain CKE low
(=0) during reset
CLKBUFOE
(CLKIN Buffer
Output Enable)
0 - CLKIN buffer disabled
1 - CLKIN buffer enabled
PHYWE (PHY Wakeup Enable)
0 - Ethernet PHY wakeup disabled
1 - Ethernet PHY wakeup enabled
Figure 20-8. Voltage Regulator Control Register
ADSP-BF537 Blackfin Processor Hardware Reference
9
8
7
0
0
0
0
0
1
0
0
9
8
7
1
0
0
0
0
0
0
1
Dynamic Power Management
6
5
4
3
2
1
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
1
0
1
1
0
1
1
0
FREQ[1:0] (Switching Frequency)
Controls the switching oscillator
frequency for the voltage regulator,
see
GAIN[1:0] (Voltage Level Gain)
Controls how quickly the voltage
output settles on its final value,
see
VLEV[3:0] (Internal Voltage Level)
See
WAKE (RTC/Reset Wakeup
Enable)
0 - RTC and Reset wakeups disabled
1 - RTC and Reset wakeups enabled
CANWE (CAN Wakeup
Enable)
0 - CAN RX wakeup disabled
1 - CAN RX wakeup enabled
Reset = 0x0200
LOCKCNT[15:0]
Number of SCLK cycles
before PLL Lock Count
timer expires.
Reset = 0x40DB
Table 20-8
for encodings
Table 20-9
for encodings
Table 20-10
for encodings
20-27
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