Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 1148

indirect branches.
Jump or call/return instructions that use a dynamic address from the data
address generator, evaluated at runtime.
input clock.
Device that generates a steady stream of timing signals to provide the fre-
quency, duty cycle, and stability to allow accurate internal clock
multiplication via the phase locked loop (PLL) module.
internal memory bank.
There are up to 4 internal memory banks on a given SDRAM. Each of
these banks can be accessed with the bank select lines BA[1:0]. The bank
address can be thought of as part of the row address
interrupt.
An event that suspends normal processing and temporarily diverts the flow
of control through an interrupt service routine (ISR). See ISR.
invalid.
Describes the state of a cache line. When a cache line is invalid, a cache
line match cannot occur.
IrDA (Infrared Data Association).
A nonprofit trade association that established standards for ensuring the
quality and interoperability of devices using the infrared spectrum.
isochronous.
Processes where data must be delivered within certain time constraints.
G-12 ADSP-BF537 Blackfin Processor Hardware Reference