Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 306

SDC Functional Description
sequence to be run, which programs the SDRAM's mode register with
burst length, burst type, and CAS latency from the
and optionally the content to the extended mode register. This initial read
or write to SDRAM takes many cycles to complete.
While executing an MRS command, the unused address pins are set to 0.
During the two clock cycles following the MRS command (t
SDC issues only NOP commands.
Extended Mode Register Set Command (Mobile SDRAM)
The extended mode register is a subset of the mode register. The EBIU
enables programming of the extended mode register during powerup via
the bit in the
EMREN
The extended mode register is initialized with these parameters:
• Partial array self-refresh, bits
programmable in
• Temperature compensated self-refresh, bits
1, bit
A[4]
• Drive strength control, bits
• Bits
A[12–7]
Not programming the extended mode register upon initialization
results in default settings for the low-power features. The extended
mode defaults with the temperature sensor enabled, full drive
strength, and full array refresh.
6-50
register.
EBIU_SDGCTL
A[2–0]
EBIU_SDGCTL
programmable in
EBIU_SDGCTL
A[6–5]
, always 0, and bit
ADSP-BF537 Blackfin Processor Hardware Reference
EBIU_SDGCTL
, bit always 0, bits
A[2]
A[4–3]
, always 0
always 1
A[13]
register
), the
MRD
A[1–0]
, bit always
A[3]