Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 327

• Bank precharge delay (
The
TRP
(
EBIU_SDGCTL
clock cycles may be selected. For example:
•
TRP = 000
No effect
•
TRP = 001
1 clock cycle
•
TRP = 010
2 clock cycles
•
TRP = 111
7 clock cycles
• RAS to CAS delay (
The
TRCD
(
EBIU_SDGCTL
clock cycles may be selected. For example:
•
TRCD = 000
•
TRCD = 001
1 clock cycle
•
TRCD = 010
2 clock cycles
•
TRCD = 111
7 clock cycles
ADSP-BF537 Blackfin Processor Hardware Reference
TRP
bits in the SDRAM memory global control register
) select the t
RP
)
TRCD
bits in the SDRAM memory global control register
) select the t
RCD
Reserved, no effect
External Bus Interface Unit
)
value. Any value between 1 and 7
value Any value between 1 and 7
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