Sdc Overview And Features - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

start: R0 = b[p0++](z);
end: b[p1++] = R0;

SDC Overview and Features

The SDRAM Controller (SDC) enables the processor to transfer data to
and from Synchronous DRAM (SDRAM) with a maximum frequency
specified in the product data sheet. The processor supports a glueless
interface with one external bank of standard SDRAMs of 64 Mbit to
512 Mbit, with configurations x4, x8, and x16, up to a maximum total
capacity of 512M bytes of SDRAM.
Features
The EBIU SDC provides a glueless interface with standard SDRAMs. Fea-
tures include:
• I/O width 16-bit, I/O supply 2.5 or 3.3 V
• Maximum throughput of 266 M bytes/second
• Supports up to 512M byte of SDRAM in external bank
• Types of 64, 128, 256, and 512M bit with I/O of x4, x8, and x16
• Supports SDRAM page sizes of 512 byte, 1K , 2K , and 4K byte
• Supports multibank operation within the SDRAM
• Supports mobile SDRAMs
• SDC uses no-burst mode (
• SDC supports 8-bit data masking writes
• SDC uses open page policy—any open page is closed only if a new
access in another page of the same bank occurs
ADSP-BF537 Blackfin Processor Hardware Reference
External Bus Interface Unit
/* byte data masking */
= ) with sequential burst type
BL 1
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