Intel ® E7501 Mch Layout Checklist; Intel ® E7501 Chipset Mch Layout Checklist - Intel Pentium M Processor Design Manual

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14.2 Intel
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Table 101. Intel E7501 Chipset MCH Layout Checklist (Sheet 1 of 4)
Checklist Items
General
Guidelines
Design Guide
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Intel Pentium
E7501 MCH Layout Checklist
Recommendations
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Intel E7501 Chipset MCH General Layout Recommendations
• 5 on 15 mils (1:3) spacing is maintained
for Data/Strobe/CMD signals; 5 on 7.5
mils (1:1.5) spacing is maintained for
CMDCLK_x/CMDCLK_x# signals.
• When using the recommended stack-up,
outer layer routing of DDR signals should
be kept to a minimum (except for
reference voltages). Via up close to
passive devices, and immediately via
back down following the device.
• Try to maintain same ground reference
when transitioning layers—add stitching
via when reference plane changes.
• Connect termination resistors directly to
termination plane (flood is on outer
layer).
• Space traces out as much as possible
through the DIMMs.
• Group like signals together under the
MCH such as ground, 1.2 V, 2.5 V, etc.
• Ensure power and ground fills are placed
directly under the processor.
• Minimize signal parallelism
• Do not share vias.
• Maintain trace width. Do not neck-down.
• Ensure signals do not cross adjacent
layer plane splits.
• Connect termination resistors directly to
termination plane (flood is on outer
layer).
• Ensure package compensation is
factored into the trace lengths.
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M Processor and Intel
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E7501 Chipset Platform
Layout Checklist
Comments
Section 12.9.1.
Section 12.9.2.
Section 12.9.3.
Section 12.9.4.
Section 12.9.5.
Section 12.9.6.
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