82547Gi(Ei) Controller Power Supply Filtering; 82547Gi(Ei) Controller Power Management And Wake Up - Intel 82562EZ Design Manual

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
Instead of using external regulators to supply 1.2 V and 1.8 V, the designer can use power
transistors in conjunction with on-chip regulation circuitry. See the reference schematic for an
implementation example.
The 82547GI(EI) controller has a LAN_PWR_GOOD input. Treat this signal as an external device
reset which works in conjunction with the internal power-on reset circuitry. In the situation where a
central power supply furnishes all the voltage sources, LAN_PWR_GOOD can possibly be tied to
the POWER_GOOD output of the power supply. Designs that generate some of the voltages
locally can connect LAN_PWR_GOOD to a power monitor chip. Ensure that the system drives
LAN_PWR_GOOD inactive for at least 80 ms after power-up.
The power sources are all expected to ramp up during a brief power-up interval (approximately 20
ms.) with LAN_PWR_GOOD de-asserted. Do not leave the 82547GI(EI) controller in a prolonged
state where some, but not all, voltages are applied.
3.3.6

82547GI(EI) Controller Power Supply Filtering

Provide several bypass capacitors for each power rail, selecting values in the range of 0.01µF to
0.01 µF. If possible, orient the capacitors close to the device and adjacent to power pads.
Decoupling capacitors should connect to the power planes with short, thick (15 mils - 0.4mm or
more) traces and 14 mil (0.35 mm) vias.
Furnish approximately 20 µF of bulk capacitance for each of the main 1.2 V and 1.8 V levels. A
convenient way to do this is to use about two 10 µF capacitors, placing them as close to the device
power connections as possible.
3.3.7

82547GI(EI) Controller Power Management and Wake Up

The 82547GI(EI) Gigabit Ethernet Controller supports low power operation as defined in the PCI
Bus Power Management Specification. There are two defined power states, D0 and D3. The D0
state provides full power operation and is divided into two sub-states: D0u (uninitialized) and D0a
(active). The D3 state provides low power operation and is also divided into two sub-states: D3hot
and D3cold.
To enter the low power state, the software driver must stop data transmission and reception. Either
the operating system or the driver must program the Power Management Control/Status Register
(PMCSR) and the Wakeup Control Register (WUC). If wakeup is desired, the appropriate wakeup
LAN address filters must also be set. The initial power management settings are specified by
EEPROM bits.
When the 82547GI(EI) controller transitions to either of the D3 low power states, the 1.2 V, 1.8 V,
and 3.3 V sources must continue to be supplied to the device. Otherwise, it will not be possible to
use a wakeup mechanism. The AUX_POWER signal is a logic input to the 82547GI(EI) controller
that denotes auxiliary power is available. If AUX_POWER is asserted, the 82547GI(EI) device
will advertise that it supports wake up from a D3cold state.
The 82547GI(EI) device supports both Advanced Power Management (APM) wakeup and
Advanced Configuration and Power Interface (ACPI) wakeup. APM wakeup has also been known
in the past as "Wake on LAN".
Wakeup uses the PME# signal to wake the system up. PME# is an active low signal connected to a
GPIO port on the ICH5 that goes active in response to receiving a "Magic Packet", a network
wakeup packet, or link status change indication. PME# remains asserted until it is disabled through
the Power Management Control/Status Register.
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