Design And Layout Consideration For Intel 82540Ep / 82551Qm; General Intel 82562Et / 82562Em / 82551Qm / 82540Ep Differential Pair Trace Routing Considerations; Table 97. Intel 82562Et/Em Control Signals - Intel 855GM Design Manual

I/O Subsystem
The four control signals shown in the below table should be configured as follows: Test_En should be
pulled-down thru a 100-Ω resistor. The remaining 3 control signals should each be connected thru 100-
Ω series resistors to the common node "Intel 82562ET/EM _Disable" of the disable circuit.

Table 97. Intel 82562ET/EM Control Signals

Test_En
0
0
1
In addition, if the LAN Connect Interface of the ICH4-M is not used, the VccLAN1_5 and the
VccLAN3_3 are still required to be powered during normal operating states. It is acceptable to power
the VccLAN1_5 and VccLAN3_3 power pins by the same voltage source that supplies power to the
Vcc1_5 and Vcc3_3 power pins. Also, the LAN_RST# pin of the ICH4-M should be pulled-down to
GND with a 10-kΩ resistor to keep the interface disabled.
11.9.5.

Design and Layout Consideration for Intel 82540EP / 82551QM

For specific design and layout considerations for the Intel 82540EP Gigabit Ethernet Controller and the
Intel 82551QM Faster Ethernet Controller, please refer to the following documents:
• 82551QM / 82540EM Interchangeable LOM Design Application Note (AP 432) (Reference
#10565)
• 82540EP Gigabit Ethernet Controller Networking Silicon Product Preview Datasheet
• 82540EP Gigabit Ethernet Controller Specification Update
• 82540EP/82541EI & 82562EZ(EX) Dual Footprint Design Guide Application Note (AP-444)
(Reference# 12504)
11.9.6. General Intel 82562ET / 82562EM / 82551QM / 82540EP
Differential Pair Trace Routing Considerations
Trace routing considerations are important to minimize the effects of crosstalk and propagation delays
on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible
to decrease interference from other signals, including those propagated through power and ground
planes.
Observe the following suggestions to help optimize board performance.
Note: Some suggestions are specific to a 4.3-mil stack-up.
232
Isol_Tck Isol_Ti Isol_Tex
0 0 0
1 1 1
1 1 1
State
Enabled
Disabled w/ Clock (low power)
Disabled w/out Clock (lowest power)
®
Intel 855GM/855GME Chipset Platform Design Guide
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