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8.5.4 External event counter operation
The external event counter counts the number of external clock pulses to be input to the INTP0/P00/TI0 pin with
the 16-bit timer register (TM0).
TM0 is incremented each time the valid edge specified with the external interrupt mode register (INTM0) is input.
When the TM0 counted value matches the 16-bit compare register (CR00) value, TM0 is cleared to 0 and the
interrupt request signal (INTTM0) is generated.
The 16-bit compare register (CR00) must be set to a value other than 0000H (1-pulse count operation is prohibited).
The rising edge, the falling edge or both edges can be selected with bits 2 and 3 (ES10 and ES11) of INTM0.
Because operation is carried out only after the valid edge is detected twice by sampling at the cycle selected with
the sampling clock select register (SCS), noise with short pulse widths can be removed.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER
Figure 8-17. External Event Counter Configuration Diagram
TI0 Valid Edge
16-Bit Compare Register (CR00)
16-Bit Timer Register (TM0)
16-Bit Capture Register (CR01)
Internal Bus
INTTM0
Clear
OVF0
INTP0
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