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8.4 16-Bit Timer Counter Operation
8.4.1 Operation as timer interrupt
In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register
20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200.
To operate the 16-bit timer counter as a timer interrupt, the following settings are required.
• Set count values to CR20
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 8-4.
Figure 8-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TMC20
–
Caution If both the CPT201 and CPT200 flags are set to 0, the capture edge becomes setting prohibited.
When the count value of 16-bit timer register 20 (TM20) coincides with the value set to CR20, counting of TM20
continues and an interrupt request signal (INTTM20) is generated.
Table 8-3 shows the interval time, and Figure 8-5 shows the timing of the timer interrupt operation.
Caution When rewriting CR20 during count operation, be sure to follow the procedure below.
<1>
Set CR20 to interrupt disable (by setting bit 7 of interrupt mask flag register 0 (MK0) to 1).
<2>
Set inversion control of timer output data to disable (TOC20 = 0)
When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the
moment of rewrite.
TCL201
TCL200
At f
2
0
0
2
/f
X
6
0
1
2
/f
X
Other than above
Setting prohibited
Remark f
:
System clock oscillation frequency (ceramic/crystal oscillation)
X
f
: System clock oscillation frequency (RC oscillation)
CC
110
CHAPTER 8 16-BIT TIMER COUNTER
0/1
0/1
0/1
0/1
0
Table 8-3. Interval Time of 16-Bit Timer Counter
Count Clock
= 5.0 MHz
At f
X
CC
(0.8 µ s)
(1.0 µ s)
2
2
/f
CC
(12.8 µ s)
(16 µ s)
6
2
/f
CC
User's Manual U13045EJ2V0UM00
0/1
0/1
Setting of count clock (see Table 8-3)
= 4.0 MHz
At f
= 5.0 MHz
X
18
2
/f
(52.4 ms)
X
22
2
/f
(838.9 ms)
X
Interval Time
At f
= 4.0 MHz
CC
18
2
/f
(65.5 ms)
CC
22
2
/f
(1,048 ms)
CC
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