Restore; Reti Instruction Processing - NEC V850/SB1 User Manual

5.2.2 Restore

Execution is restored from non-maskable interrupt servicing by the RETI instruction.
Operation of RETI instruction
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
(1) Restores the values of the PC and PSW from FEPC and FEPSW, respectively, because the EP bit of the
PSW is 0 and the NP bit of the PSW is 1.
(2) Transfers control back to the address of the restored PC and PSW.
How the RETI instruction is processed is shown below.
1
Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during non-
maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by
the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the
LDSR instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
152
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 5-3. RETI Instruction Processing
RETI instruction
PSW.EP
0
PSW.NP
0
PC EIPC
PSW EIPSW
Original processing restored
User's Manual U13850EJ6V0UD
1
PC FEPC
PSW FEPSW