Dma Transfer Requests - Hitachi SH7709S Hardware Manual

11.3.2

DMA Transfer Requests

DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by devices and on-chip peripheral modules that are neither the source
nor the destination. Transfers can be requested in three modes: auto-request, external request, and
on-chip module request. The request mode is selected in the RS3–RS0 bits of DMA channel
control registers 0–3 (CHCR0–CHCR3).
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bit of CHCR0–CHCR3 and the DME bit of
DMAOR are set to 1, the transfer begins so long as the TE bit of CHCR0–CHCR3 and the NMIF
and AE bits of DMAOR are 0.
External Request Mode: In this mode a transfer is performed in response to the request signal
(DREQ) of an external device. Choose one of the modes shown in table 11.3 according to the
application system. When this mode is selected, if DMA transfer is enabled (DE = 1, DME = 1,
TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input. Choose
DREQ detection by either a falling edge or low level of the signal input with the DS bit in CHCR0
and CHCR1 (DS = 0 for level detection, DS = 1 for edge detection). The source of the transfer
request does not have to be the data transfer source or destination.
Table 11.3 Selecting External Request Modes with RS Bits
RS3 RS2 RS1
0 0 0
1
Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral
module (This applies only to IrDA, SCIF, A/D converter, D/A converter, and I/O ports.)
On-Chip Module Request Mode: In this mode a transfer is performed in response to a transfer
request signal (interrupt request signal) of an on-chip module. This mode cannot be set in case of
16-byte transfer. These are six transfer request signals: the receive-data-full interrupts (RXI) and
the transmit-data-empty interrupts (TXI) from two serial communication interfaces (IrDA, SCIF),
the A/D conversion end interrupt (ADI) of the A/D converter, and the compare match timer
interrupt (CMI) of the CMT (table 11.4). When this mode is selected, if DMA transfer is enabled
RS0 Address Mode
0 Dual address
mode
0 Single address
mode
1
Source Destination
Any* Any*
External memory, External device with
memory-mapped DACK
external device
External device with External memory,
DACK memory-mapped
external device
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