Section 5 Interrupt Controller; Overview; Features - Hitachi H8/3006 Hardware Manual

5.1

Overview

5.1.1

Features

The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level enable/disable state setting possible by means of the I and UI bits in the CPU's
condition code register (CCR) and the UE bit in the system control register (SYSCR)
• Seven external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ
independently.

Section 5 Interrupt Controller

to IRQ , sensing of the falling edge or level sensing can be selected
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