Operation In Clear & Start Mode Entered By Ti00N Pin Valid Edge Input - NEC 78K0 Series User Manual

7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input
When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 10 (clear &
start mode entered by the TI00n pin valid edge input) and the count clock (set by PRM0n) is supplied to the
timer/event counter, TM0n starts counting up. When the valid edge of the TI00n pin is detected during the counting
operation, TM0n is cleared to 0000H and starts counting up again. If the valid edge of the TI00n pin is not detected,
TM0n overflows and continues counting.
The valid edge of the TI00n pin is a cause to clear TM0n. Starting the counter is not controlled immediately after
the start of the operation.
CR00n and CR01n are used as compare registers and capture registers.
(a) When CR00n and CR01n are used as compare registers
Signals INTTM00n and INTTM01n are generated when the value of TM0n matches the value of CR00n and
CR01n.
(b) When CR00n and CR01n are used as capture registers
The count value of TM0n is captured to CR00n and the INTTM00n signal is generated when the valid edge is
input to the TI01n pin (or when the phase reverse to that of the valid edge is input to the TI00n pin).
When the valid edge is input to the TI00n pin, the count value of TM0n is captured to CR01n and the
INTTM01n signal is generated. As soon as the count value has been captured, the counter is cleared to
0000H.
Caution Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and PRM0n0 = 11). When
PRM0n1 and PRM0n0 = 11, TM0n is cleared.
Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
3. n = 0:
n = 0, 1:
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
µ
PD78F0531, 78F0532, 78F0533
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
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