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(1) During address transmission/reception
• Slave device operation : Interrupt and wait timing are determined regardless of the WTIM bit.
• Master device operation : Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
(2) During data reception
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
(3) During data transmission
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
(4) Wait cancellation method
The two wait cancellation methods are as follows.
• By setting bit 5 (WREL) of IIC control register (IICC0) to "1"
• By writing to the IIC shift register (IIC0)
When 8-clock wait has been selected (WTIM = 0), the output level of ACK must be determined prior to wait
cancellation.
(5) Stop condition detection
INTIIC0 is generated when a stop condition is detected.
10.3.7 Address match detection method
2
When in I
C bus mode, the master device can select a particular slave device by transmitting the corresponding
slave address.
Address match detection is performed automatically by hardware. An interrupt request (INTIIC0) occurs when a
local address has been set to the slave address register (SVA0) and when the address set to SVA0 matches the
slave address sent by the master device, or when an extension code has been received.
CHAPTER 10 SERIAL INTERFACE FUNCTION
the WTIM bit.
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