Table of Contents
Advertisement
(5)
Stop condition detection
INTIICn is generated when a stop condition is detected.
Remark
n = 0, 1
10.3.7 Address match detection method
2
In I
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
address.
Address match detection is performed automatically by hardware. An interrupt request (INTIICn) occurs when a
local address has been set to slave address register n (SVAn) and when the address set to SVAn matches the slave
address sent by the master device, or when an extension code has been received (n = 0, 1).
10.3.8 Error detection
2
In I
C bus mode, the status of the serial data bus (SDAn) during data transmission is captured by IIC shift register
n (IICn) of the transmitting device, so the IICn data prior to transmission can be compared with the transmitted IICn
data to enable detection of transmission errors. A transmission error is judged as having occurred when the
compared data values do not match (n = 0, 1).
10.3.9 Extension code
(1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXCn) is set for
extension code reception and an interrupt request (INTIICn) is issued at the falling edge of the eighth clock (n =
0, 1).
The local address stored in slave address register n (SVAn) is not affected.
(2) If 11110xx0 is set to SVAn by a 10-bit address transfer and 11110xx0 is transferred from the master device, the
results are as follows. Note that INTIICn occurs at the falling edge of the eighth clock (n = 0, 1).
• Higher 4 bits of data match: EXCn = 1
• 7 bits of data match: COIn = 1
Note EXCn: Bit 5 of IIC status register n (IICSn)
COIn: Bit 4 of IIC status register n (IICSn)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
code, such processing is performed by software.
For example, when operation as a slave is not desired after the extension code is received, set bit 6 (LRELn) of
IIC control register n (IICCn) to 1 and the CPU will enter the next communication wait state.
318
CHAPTER 10
SERIAL INTERFACE FUNCTION
Note
Note
User's Manual U13850EJ6V0UD
Advertisement
Table of Contents
