Cpu Register Set - NEC PD703114 User Manual

V850e/ia2 32-bit single-chip microcontrollers
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3.2 CPU Register Set

The registers of the V850E/IA2 can be classified into two categories: a general-purpose program register set and a
dedicated system register set. The width of all the registers is 32 bits.
For details, refer to V850E1 Architecture User's Manual.
(1) Program register set
31
r0
(Zero register)
r1
(Assembler-reserved register)
r2
r3
(Stack pointer (SP))
r4
(Global pointer (GP))
r5
(Text pointer (TP))
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
(Element pointer (EP))
r31
(Link pointer (LP))
31
PC
(Program counter)
CHAPTER 3 CPU FUNCTION
(2) System register set
0
31
EIPC
EIPSW
FEPC
FEPSW
ECR
PSW
CTPC
CTPSW
DBPC
DBPSW
CTBP
0
User's Manual U15195EJ5V0UD
(Status saving register during interrupt)
(Status saving register during interrupt)
(Status saving register during NMI)
(Status saving register during NMI)
(Interrupt source register)
(Program status word)
(Status saving register during CALLT execution)
(Status saving register during CALLT execution)
(Status saving register during exception/debug trap)
(Status saving register during exception/debug trap)
(CALLT base pointer)
0
47

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