Cpu Register Set - NEC V850E/RS1 User Manual

3.2 CPU Register Set

The CPU registers of the V850E/RS1 can be classified into general purpose register set, which are
used by programs, and system register set, which are used to control the execution environment. This
chapter describe also specific registers which can be read or written using the LDSR and STSR instruc-
tions. All the registers have 32-bit width.
For details, refer to V850E1 User's Manual Architecture.
(Document No. U14559EJ2V0UM00 (2nd edition))
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r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
31
PC
62
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Figure 3-1: CPU Register Set
(1) Program register set
(Zero register)
(Assembler-reserved register)
(Stack pointer (SP))
(Global pointer (GP))
(Text pointer (TP))
(Element pointer (EP))
(Link pointer (LP))
(Program counter)
User's Manual U16702EE3V2UD00
Chapter 3 CPU Function
0 31
EIPC (Interrupt status saving register)
EIPSW (Interrupt status saving register)
FEPC (NMI status saving register)
FEPSW (NMI status saving register)
ECR (Interrupt source register)
PSW
CTPC
CTPSW
DBPC
DBPSW
CTBP
0
(2) System register set
(Program status word)
(CALLT execution status saving register)
(CALLT execution status saving register)
(Exception/debug trap status saving register)
(Exception/debug trap status saving register)
(CALLT base pointer)
0