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3.2.2
Reset by Watchdog Timer
When the watchdog timer overflows, the chip enters the reset state and reset exception handling
begins. The same reset exception handling is carried out as for input at the RES pin. For details on
the watchdog timer, see section 13, Watchdog Timer.
3.2.3
Interrupt Immediately after Reset
After a reset, if the CPU was to accept an interrupt before the stack pointer (SP) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in control over the program
being lost. To prevent this, immediately after reset exception handling all interrupts including
NMI are masked. For this reason, the initial program instruction is always executed immediately
after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
RES
ø
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
50
Reset cleared
Vector fetch
Figure 3.1 Reset Sequence
Initial program
instruction prefetch
Internal
processing
(1)
(2)
(2)
(3)
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