Chip-Select Address Range; Chip Select Address Range; Eim Interface Example - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

If MOD is driven to a logic-low level four LOW_REFCLK clock cycles before RSTOUT
negation, and the CSEN0 bit is enabled (the default state on reset), then the internal
ROM is disabled, and CS0 is asserted for the first CPU access. The internal ROM is
disabled for the first CPU access only and is available for subsequent accesses. The
CS0 access uses default values of 15 wait states and a 16-bit port size.
7.2.6.2 Chip Select 1–2 (CS[1:2])
These active-low output signals are asserted based on a decode of bits ADDR[31:24]
of the access address. When disabled, these pins can be used as programmable
general-purpose outputs.
7.2.6.3 Chip Select 3 (CS3)
This active-high output signal is asserted based on a decode of the internal address
bus bits ADDR[31:24] of the access address. When disabled, this pin can be used as
a programmable general-purpose output.

7.3 Chip-Select Address Range

Table 7-1 specifies the address range for each chip select output.
CSENx
Cleared
Set
Set
Set
Set

7.4 EIM Interface Example

Figure 7-2 shows an example of an EIM interface to memory and peripherals.
MMC2001
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Table 7-1 Chip Select Address Range
ADDR[31:24]
—
00101101
00101111
00101110
00101100
EXTERNAL INTERFACE MODULE
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Chip Select Typical Use
Inactive —
CS0 Flash
CS1 SRAM
CS2 Spare
CS3 LCD
MOTOROLA
7-3