Interface Requirements For Read And Write Cycles - Motorola M-CORE MMC2001 Series Reference Manual

The M•CORE receives a clock input (CLK) from an external clock source and gener-
ates two internal clocks (C1 and C2). The CLK input sets the frequency of operation
for the bus interface directly. The clock source monitors the M•CORE low power mode
outputs (LPMD[1:0]) and controls the clock input to the M•CORE accordingly by forc-
ing the clocks low for low-power operation.
Data transfers occur between an internal register and the external bus. The internal
register connects to the external data bus through the internal data bus and a data
multiplexer. The data multiplexer establishes the necessary connections for different
combinations of address and data sizes. This multiplexer is physically positioned in
the overall system to minimize power consumption by minimizing loading and reduc-
ing unnecessary signal transitions. Logically, however, it is considered part of the
M•CORE.
The M•CORE does not support dynamic bus sizing and expects the referenced
device to accept the requested access width. Peripherals with an interface width of N
bits should not define internal registers greater than N bits wide.
Misaligned transfers are not supported. The M•CORE interface may drive the
ADDR[1:0] address lines to a value which is not representative of an aligned transfer,
but expects aligned data to be transferred. ADDR[1:0] should be selectively ignored
by external logic, depending on the size of the transfer.
The data multiplexer takes the four bytes of the core interface data bus and routes
them to their required positions to interface properly to memory or peripherals. The
external multiplexer connections to memory are controlled on a byte granularity and
are referred to as MB0–MB3, where MB0 resides at byte address 0 (mod 4) and MB3
resides at byte address 3 (mod 4). For example, MB0 would normally be routed to
DATA[31:24] on a word transfer, but it can also be routed to DATA[7:0] for supporting a
byte data transfer. The same is true for any of the other operand bytes.
Figure 2-6 shows the connection requirements for the multiplexer. The transfer size
(TSIZ[1:0]) and byte offset (ADDR1 and ADDR0) signals determine the positioning of
the bytes (see Table 2-3).
Table 2-3 Interface Requirements for Read and Write Cycles
Transfer
Size
TSIZ1 TSIZ0 ADDR1 ADDR0 DATA[31:24] DATA[23:16] DATA[15:8]
0 1
0 1
Byte
0 1
0 1
1 0
Halfword
1 0
Word 0 0
MOTOROLA
2-12
Freescale Semiconductor, Inc.
Active Interface Bus Sections
0 0 —
0 1 —
1 0 —
1 1 —
0 X —
1 X —
X X MB0
INTEGER CPU
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DATA[7:0]
— —
— —
— —
— —
— MB0
— MB2
MB1 MB2
Mux
Connections
MB0 a
MB1 b
MB2 c
MB3 d
MB1 e
MB3 f
MB3 g
MMC2001
REFERENCE MANUAL