Table 3-8. Memory Range Register Signal Encoding; Table 3-9. Did[7:0]# Encoding - Intel Pentium Pro Family Developer's Manual

BUS OVERVIEW
The ATTR[7:0]# pins describe the cache attributes. They are driven based on the Memory Type
Range Register attributes and the Page Table attributes as described in Table 3-8. See Chapter 6,
Range Registers for a description of the memory types.

Table 3-8. Memory Range Register Signal Encoding

ATTR[7:0]#
00000000
00000100
00000101
00000110
00000111
All others
The DID[7:0]# signals contain the request agent ID on bits DID[6:4]#, the transaction ID on
DID[3:0]#, and the agent type on DID[7]#. Symmetric agents use an agent type of 0. All priority
agents use an agent type of 1. Every deferrable transaction (DEN# asserted) issued on the Pen-
tium Pro processor bus which has not been guaranteed completion will have a unique Deferred
ID. After one of these transactions passes its Snoop Result Phase without DEFER# asserted, its
Deferred ID may be reused. During a deferred reply transaction, the Deferred ID of the agent
that deferred the original transaction is driven instead of an address.
DID[7]#
Agent Type
The Byte Enables BE[7:0]# are used to determine which bytes of data should be transferred if
the data transfer is less than 8 bytes wide. BE7# applies to D[63:56], BE0# applies to D[7:0].
The byte enables are also used for special transaction encoding (see Table 3-10).
3-16
Memory Type
UC
WC
WT
WP
WB
Reserved

Table 3-9. DID[7:0]# Encoding

DID[6:4]#
Agent ID
Description
UnCacheable
Write-combining
WriteThrough
WriiteProtect
WriteBack
DID[3:0]#
Transaction ID