Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 121

Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
11
10
9:7
6
5:5
4
Datasheet, Volume 2
0/1/0–2/PCI
D0–D1h
0002h
RWS, RWS-V
16 bits
0h
Reset RST/
Attr
Value PWR
Powerg
RWS 0b
ood
Powerg
RWS 0b
ood
Powerg
RWS-V 000b
ood
Powerg
RWS 0b
ood
RO 0h
Powerg
RWS 0b
ood
Description
Compliance SOS (compsos)
When set to 1b, the TXTSSM is required to send SKP Ordered Sets
periodically in between the (modified) compliance patterns. For a
Multi-Function device associated with an Upstream Port, the bit in
Function 0 is of type RWS, and only Function 0 controls the
component's Link behavior. In all other Functions of that device,
this bit is of type RsvdP. The Reset Value of this bit is 0b.
Components that support only the 2.5 GT/s speed are permitted to
hardwire this field to 0b.
Enter Modified Compliance (entermodcompliance)
When this bit is set to 1b, the device transmits modified
compliance pattern if the TXTSSM enters Polling.Compliance state.
Components that support only the 2.5GT/s speed are permitted to
hardwire this bit to 0b.
Transmit Margin (txmargin)
This field controls the value of the non-deemphasized voltage level
at the Transmitter pins. This field is reset to 000b on entry to the
TXTSSM Polling.Configuration substate.
Encodings:
000 = Normal operating range
001 = 800–1200 mV for full swing and 400–700 mV for
half-swing
010 - (n-1) = Values must be monotonic with a non-zero slope.
The value of n must be greater than 3 and less than
7.
At least two of these must be below the normal
operating range
n = 200–400 mV for full-swing and 100–200 mV for
half-swing
n -111 = Reserved
Reset Value is 000b.
Components that support only the 2.5 GT/s speed are permitted to
hardwire this bit to 0b.
When operating in 5 GT/s mode with full swing, the de-emphasis
ratio must be maintained within +/- 1dB from the spec defined
operational value (either -3.5 or -6 dB).
Selectable De-emphasis (selectabledeemphasis)
When the Link is operating at 5GT/s speed, selects the level of de-
emphasis. Encodings:
1 = -3.5 dB
0 = -6 dB
Reset Value is implementation specific, unless a specific value is
required for a selected form factor or platform.
When the Link is operating at 2.5 GT/s speed, the setting of this bit
has no effect. Components that support only the 2.5 GT/s speed
are permitted to hardwire this bit to 0b.
Reserved
Enter Compliance (EC)
Software is permitted to force a link to enter Compliance mode at
the speed indicated in the Target Link Speed field by setting this bit
to 1b in both components on a link and then initiating a hot reset
on the link.
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