Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 51

Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
10:9
8
7
6:6
5
4
3:0
Datasheet, Volume 2
0/0/0/PCI
6–7h
0090h
RO, RW1C
16 bits
00h
Reset RST/
Attr
Value PWR
RO 00b Uncore
RW1C 0b Uncore
RO 1b Uncore
RO 0h
RO 0b Uncore
RO 1b Uncore
RO 0h
Description
DEVSEL Timing (DEVT)
These bits are hardwired to "00". Writes to these bit positions have
no effect. Device 0 does not physically connect to PCI_A. These
bits are set to "00" (fast decode) so that optimum DEVSEL timing
for PCI_A is not limited by the Host.
Master Data Parity Error Detected (DPD)
This bit is set when DMI received a Poisoned completion from PCH.
This bit can only be set when the Parity Error Enable bit in the PCI
Command register is set.
Fast Back-to-Back (FB2B)
This bit is hardwired to 1. Writes to these bit positions have no
effect. Device 0 does not physically connect to PCI_A. This bit is
set to 1 (indicating fast back-to-back capability) so that the
optimum setting for PCI_A is not limited by the Host.
Reserved
66 MHz Capable (MC66)
Does not apply to PCI Express. Must be hardwired to 0.
Capability List (CLIST)
This bit is hardwired to 1 to indicate to the configuration software
that this device/function implements a list of ne w capabilities. A list
of new capabilities is accessed using register CAPPTR at
configuration address offset 34h. Register CAPPTR contains an
offset pointing to the start address within configuration space of
this device where the Capability Identification register resides.
Reserved
51