Intel Itanium 2 Processor Datasheet
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Intel Itanium 2 Processor Datasheet

Intel Itanium 2 Processor Datasheet

2 processor 1.66 ghz with 9 mb l3 cache / 1.66 ghz with 6 mb l3 cache / 1.6 ghz with 9 mb l3 cache / 1.6 ghz with 6 mb l3 cache/ 1.5 ghz with 6 mb l3 cache / 1.5 ghz with 4 mb l3 cache / 1.4 ghz with 4 mb l3 cache / 1.3 ghz with 3 mb l3 cache / 1.0 ghz wi
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®
Intel
Itanium
®
®
Intel
Itanium
2 Processor 1.66 GHz with 9 MB L3 Cache
®
®
Intel
Itanium
2 Processor 1.66 GHz with 6 MB L3 Cache
®
®
Intel
Itanium
2 Processor 1.6 GHz with 9 MB L3 Cache
®
®
Intel
Itanium
2 Processor 1.6 GHz with 6 MB L3 Cache
®
®
Intel
Itanium
2 Processor 1.5 GHz with 6 MB L3 Cache
®
®
Intel
Itanium
2 Processor 1.5 GHz with 4 MB L3 Cache
®
®
Intel
Itanium
2 Processor 1.4 GHz with 4 MB L3 Cache
®
®
Intel
Itanium
2 Processor 1.3 GHz with 3 MB L3 Cache
®
®
Intel
Itanium
2 Processor 1.0 GHz with 3 MB L3 Cache
®
®
Intel
Itanium
2 Processor 900 MHz with 1.5 MB L3 Cache
Datasheet
February 2006
®
2 Processor
Document Number: 250945-005

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Summary of Contents for Intel Itanium 2 Processor

  • Page 1 ® ® Intel Itanium ® ® Intel Itanium 2 Processor 1.66 GHz with 9 MB L3 Cache ® ® Intel Itanium 2 Processor 1.66 GHz with 6 MB L3 Cache ® ® Intel Itanium 2 Processor 1.6 GHz with 9 MB L3 Cache ®...
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548- 4725, or by visiting Intel's website at http://www.intel.com.

  • Page 3: Table Of Contents

    Contents Introduction... 11 Overview ... 11 Processor Abstraction Layer ... 11 Mixing Processors of Different Frequencies and Cache Sizes ... 12 Terminology... 12 State of Data ... 12 Reference Documents... 13 Electrical Specifications... 15 ® Itanium 2.1.1 System Bus Power Pins ... 15 2.1.2 System Bus No Connect ...
  • Page 4 6.1.3 SMBus Device Addressing... 81 Processor Information ROM... 82 Scratch EEPROM ... 85 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions ... 85 Thermal Sensing Device ... 86 Thermal Sensing Device Supported SMBus Transactions ... 87 Thermal Sensing Device Registers ... 88 6.7.1 Thermal Reference Registers ...
  • Page 5 A.1.37 ID[9:0]# (I) ...99 A.1.38 IDS# (I) ... 99 A.1.39 IGNNE# (I)...100 A.1.40 INIT# (I) ...100 A.1.41 INT (I) ...100 A.1.42 IP[1:0]# (I)...100 A.1.43 LEN[2:0]# (I/O) ...100 A.1.44 LINT[1:0] (I) ...101 A.1.45 LOCK# (I/O) ...101 A.1.46 NMI (I) ...101 A.1.47 OWN# (I/O) ...101 A.1.48 PMI# (I)...101 A.1.49 PWRGOOD (I)...101 A.1.50 REQ[5:0]# (I/O) ...101...
  • Page 6 ® Itanium Logical Schematic of SMBus Circuitry ... 80 Tables ® Itanium ® Itanium ® Itanium AGTL+ Signals DC Specifications... 18 Power Good Signal DC Specifications ... 19 System Bus Clock Differential HSTL DC Specifications ... 19 TAP Connection DC Specifications... 19 SMBus DC Specifications ...
  • Page 7 Thermal Sensing Device SMBus Addressing on the Itanium EEPROM SMBus Addressing on the Itanium Processor Information ROM Format ... 82 Current Address Read SMBus Packet ... 86 Random Address Read SMBus Packet ... 86 Byte Write SMBus Packet ... 86 Write Byte SMBus Packet ...

  • Page 8: Revision History

    Initial release of this document. -002 Updated content to include information pertaining to Itanium 2 processor (1.5 GHz, 6 MB), Itanium 2 processor (1.4 GHz, 4 MB) and Itanium 2 processor (1.3 GHz, 3 MB). -003 Updated content to include information pertaining to Itanium processor (1.5 GHz, 4 MB) and Itanium 2 processor (1.6 GHz, 6 MB and...

  • Page 9: Product Features

    Microsoft Windows*, HP-UX* and Linux*. The Itanium 2 processor is designed to support very large scale systems, including those employing thousands of processors, to provide the processing power and performance head room for the most demanding enterprise and technical computing applications.
  • Page 10 Datasheet...

  • Page 11: Introduction

    This strategy increases the synergy between hardware and software, and leads to greater overall performance. The Itanium 2 processor provides a 6-wide and 8-stage deep pipeline, running at up to 1.66 GHz. This provides a combination of abundant resources to exploit ILP as well as increased frequency for minimizing the latency of each instruction.

  • Page 12: Mixing Processors Of Different Frequencies And Cache Sizes

    , or a capitalized abbreviated subscript, for example, T CC,core State of Data The data contained in this document is subject to change. It is the best information that Intel is able to provide at the publication date of this document. Datasheet...

  • Page 13: Reference Documents

    ® Intel Itanium Processor Family System Abstraction Layer Specification ITP700 Debug Port Design Guide System Management Bus Specification Note: Contact your Intel representative or check http://developer.intel.com for the latest revision of the reference documents. Datasheet Title Introduction Document Number 251141...
  • Page 14 Introduction Datasheet...

  • Page 15: Electrical Specifications

    AGTL+ inputs use differential receivers which require a reference signal (V the receivers to determine if a signal is a logical 0 or a logical 1. The Itanium 2 processor generates on-die, thereby eliminating the need for an off-chip reference voltage source.

  • Page 16: Signal Descriptions

    The TAP Connection Output signals are AGTL+ output signals. The Itanium 2 processor system bus requires termination on both ends of the bus. The Itanium 2 processor system bus supports both on-die and off-die termination controlled by two pins, TERMA and TERMB.

  • Page 17: Package Specifications

    VCCMON, VSSMON Package Specifications Table 2-2 through Table 2-9 processor. The voltage and current specifications are defined at the Itanium 2 processor pins. Operational specifications listed in specifications for case temperature, clock frequency, and input voltages. ® Table 2-2. Itanium...

  • Page 18: Signal Specifications

    5. Maximum thermal design envelope is provided for the design of thermal/chassis solutions. 6. Maximum thermal design power is an estimate of the power dissipation for the Itanium 2 processor offering while executing a worst-case application mix under nominal V ®...

  • Page 19: Power Good Signal Dc Specifications

    Table 2-4. AGTL+ Signals DC Specifications (Sheet 2 of 2) Symbol Leakage Current AGTL+ Pad Capacitance AGTL+ NOTES: 1. The typical transition point between V ±100 mV respectively, for a system bus agent using on-board termination. V mV respectively, for a system bus agent using on-die termination. 2.

  • Page 20: Smbus Dc Specifications

    THRMALERT#. applies only to THRMALERT# which is an open drain signal. Parameter Minimum Table 2-11 list the AC specifications for the Itanium 2 processor’s clock and Figure 2-1). The Itanium 2 processor uses a differential HSTL System Minimum...

  • Page 21: Smbus Ac Specifications

    Table 2-10. System Bus Clock Differential HSTL AC Specifications (Sheet 2 of 2) Symbol Parameter BCLKp Low Time BCLKp Period period System Clock Skew skew BCLKp Frequency BCLK BCLKp Input Jitter jitter BCLKp High Time high BCLKp Low Time BCLKp Rise Time rise BCLKp Fall Time fall...

  • Page 22: Maximum Ratings

    Maximum Ratings Table 2-12 contains the Itanium 2 processor stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are given in the DC tables.

  • Page 23: System Bus Signal Quality Specifications And Measurement Guidelines

    Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the Itanium 2 processor, both are referenced to GND as shown in important to note that overshoot and undershoot conditions are separate and their impact must be determined independently.

  • Page 24: Overshoot/Undershoot Pulse Duration

    Electrical Specifications Figure 2-3. System Bus Signal Waveform Exhibiting Overshoot/Undershoot CTERM 2.5.2 Overshoot/Undershoot Pulse Duration Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/undershoot reference voltage (V oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration.

  • Page 25: Reading Overshoot/Undershoot Specification Tables

    4. Ringback below VCTERM cannot be subtracted from overshoots/undershoots. 5. Lesser undershoot does not allocate overshoot with longer duration or greater magnitude. 6. OEM’s are strongly encouraged to follow Intel layout guidelines. 7. All values specified by design characterization. 2.5.5...

  • Page 26: Source Synchronous Agtl+ Signal Group And Wired-Or Signal Group Absolute Overshoot/Undershoot Tolerance

    Electrical Specifications 3. If multiple overshoots and/or multiple undershoots occur, measure the worst-case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst-case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where AF = 1), then the system passes.

  • Page 27: Signal Group Time-Dependent Overshoot/Undershoot Tolerance

    ® Table 2-15. Itanium 2 Processors (1.5 GHz/4 MB, 1.6 GHz) Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/Undershoot Tolerance for 400 MHz System Bus Absolute Maximum (V) Over- Under- shoot shoot –0.6 1.75 –0.55 –0.5 1.65 –0.45 –0.4 1.55 –0.35 –0.3 1.45 –0.25...

  • Page 28: Binit#, Hit#, Hitm#, Bnr#, Tnd#, Berr Overshoot/Undershoot Tolerance For 400 Mhz System Bus

    Electrical Specifications ® Table 2-17. Itanium 2 Processors (1.66 GHz) Source Synchronous AGTL+ Signal Group Time-Dependent Overshoot/Undershoot Tolerance for 667 MHz System Bus Absolute Maximum (V) Over- Under- shoot shoot –0.6 1.75 –0.55 –0.5 1.65 –0.45 –0.4 1.55 –0.35 –0.3 1.45 –0.25 NOTES:...
  • Page 29 ® Table 2-19. Itanium 2 Processors (1.5 GHz/4 MB, 1.6 GHz) Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#, BERR#) Overshoot/Undershoot Tolerance for 400 MHz System Bus Absolute Maximum (V) Over- Under- shoot shoot –0.6 1.75 –0.55 –0.5 1.65 –0.45 –0.4 1.55 –0.35...

  • Page 30: Power Pod Connector Signals

    1. Activity Factor = 1 means signal toggles every 6 ns. Power Pod Connector Signals Power delivery for the Itanium 2 processor is from a DC-DC converter called the “power pod”. The power pod consists of a DC-DC converter and a semi-flexible connector which delivers the voltage to the processor.

  • Page 31: Processor Core Voltage Identification Code

    3.3 V power supply. The VID pads on the power connector tab will be pulled low with 10 Ω resistors that are internal to the processor. The 10 Ω resistive pulldowns are controlled by Intel and will not be externally adjustable. Table 2-23. Processor Core Voltage Identification Code Processor Pins: 0 = Connected to GND;...

  • Page 32: Itanium ® 2 Processor System Bus Clock And Processor Clocking

    All Itanium 2 processor system bus timing parameters are specified with respect to the falling edge of BCLKn and rising edge of BCLKp. The Itanium 2 processor core to bus ratio must be configured during system reset by using the A[21:17]# pins (see these pins during the system reset sequence determines the multiplier that the PLL will use for the internal core clock.
  • Page 33 • The Itanium 2 processor 900 MHz with 1.5 MB L3 cache supports a bus ratio of 2/9. • The Itanium 2 processor 1.0 GHz with 3 MB L3 cache supports a bus ratio of 2/10.

  • Page 34: System Bus Reset And Configuration Timings For Cold Reset

    Electrical Specifications Figure 2-6. System Bus Reset and Configuration Timings for Cold Reset BCLK PWRGOOD RESET# Bus Ratio (A[21:17]#) Additional Configuration Signals = 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#) = 1 ms minimum for cold reset = Bus ratio signals must be asserted no later than RESET# = 2 BCLKs minimum, 3 BCLKs maximum = 4 BCLKs minimum...

  • Page 35: Recommended Connections For Unused Pins

    Figure 2-7. System Bus Reset and Configuration Timings for Warm Reset BCLK PWRGOOD RESET# Bus Ratio (A[21:17]#) Additional Configuration Signals = 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#) = 1 ms minimum for warm reset = Bus ratio signals must be asserted no later than RESET# = 2 BCLKs minimum, 3 BCLKs maximum = 4 BCLKs minimum...
  • Page 36 Electrical Specifications Table 2-26. Connection for Unused Pins (Sheet 2 of 2) Pins/Pin Groups System Management Signals 3.3V SMA[2:0] SMSC SMSD SMWP THRMALERT# LVTTL Power Pod Signals OUTEN PPODGD# CPUPRES# Reserved Pins NOTES: 1. L = GND, H = V CTERM 2.

  • Page 37: Pinout Specifications

    Pinout Specifications This chapter describes the Itanium 2 processor signals and pinout. Note: The pins labeled “N/C” must remain unconnected. The Itanium 2 processor uses a JEDEC standard pin naming convention. In this chapter, pin names are the actual names given to each physical pin of the processor.

  • Page 38: Pin/Signal Information Sorted By Pin Name

    Pinout Specifications Table 3-1 provides the Itanium 2 processor pin list in alphabetical order. Table 3-2 provides the Itanium 2 processor pin list by pin location. Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 1 of 15) Pin Name 3.3V...
  • Page 39 Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 2 of 15) Pin Name A040# A041# A042# A043# A044# A045# A046# A047# A048# A049# A20M# ADS# AP0# AP1# BCLKn BCLKp BERR# BINIT# BNR# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPRI# BR0# BR1# BR2#...
  • Page 40 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 3 of 15) Pin Name D010# D011# D012# D013# D014# D015# D016# D017# D018# D019# D020# D021# D022# D023# D024# D025# D026# D027# D028# D029# D030# D031# D032# D033# D034# D035# D036#...
  • Page 41 Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 4 of 15) Pin Name D051# D052# D053# D054# D055# D056# D057# D058# D059# D060# D061# D062# D063# D064# D065# D066# D067# D068# D069# D070# D071# D072# D073# D074# D075# D076# D077# D078# D079#...
  • Page 42 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 5 of 15) Pin Name D092# D093# D094# D095# D096# D097# D098# D099# D100# D101# D102# D103# D104# D105# D106# D107# D108# D109# D110# D111# D112# D113# D114# D115# D116# D117# D118#...
  • Page 43 Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 6 of 15) Pin Name DEP01# DEP02# DEP03# DEP04# DEP05# DEP06# DEP07# DEP08# DEP09# DEP10# DEP11# DEP12# DEP13# DEP14# DEP15# DRDY# DRDY0# DRDY1# FERR# Datasheet System Bus Input/Output Signal Name Location DEP1# DEP2# DEP3#...
  • Page 44 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 7 of 15) Pin Name System Bus Input/Output Signal Name Location AB19 AB21 AB23 AB25 AC02 AC24 AD01 AD03 AD05 AD07 AD09 AD11 AD13 AD15 AD17 AD19 AD21 AD23 AD25 AE02 AE24...
  • Page 45 Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 8 of 15) Pin Name Datasheet System Bus Input/Output Signal Name Location AG22 AG24 AH01 Pinout Specifications Notes...
  • Page 46 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 9 of 15) Pin Name System Bus Input/Output Signal Name Location Notes Datasheet...
  • Page 47 Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 10 of 15) Pin Name Datasheet System Bus Input/Output Signal Name Location Pinout Specifications Notes...
  • Page 48 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 11 of 15) Pin Name GSEQ# HIT# HITM# ID0# System Bus Input/Output Signal Name Location GSEQ# AD14 HIT# AB10 HITM# AB12 IDA0#/IP0# AD02 Notes IN/OUT IN/OUT Datasheet...
  • Page 49 Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 12 of 15) Pin Name ID1# ID2# ID3# ID4# ID5# ID6# ID7# ID8# ID9# IDS# IGNNE# INIT# LINT0 LINT1 LOCK# Datasheet System Bus Input/Output Signal Name Location IDA1#/IP1# AB02 IDA2#/DHIT# AC03 IDA3#/IDB3# AA03 IDA4#/IDB4#...
  • Page 50 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 13 of 15) Pin Name OUTEN PMI# PPODGD# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# REQ5# RESET# RS0# RS1# RS2# RSP# SBSY# SBSY0# SBSY1# SMA0 SMA1 SMA2 SMSC SMSD SMWP STBN0# STBN1# STBN2#...
  • Page 51 Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 14 of 15) Pin Name STBP2# STBP3# STBP4# STBP5# STBP6# STBP7# TERMA TERMB THRMTRIP# THRMALERT# TND# TRDY# TRST# TUNER[1] TUNER[2] VCCMON VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM...
  • Page 52 Pinout Specifications Table 3-1. Pin/Signal Information Sorted by Pin Name (Sheet 15 of 15) Pin Name VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM VCTERM...

  • Page 53: Pin/Signal Information Sorted By Pin Location

    Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 1 of 15) Pin Name VCTERM VCTERM THRMALERT# VSSMON VCTERM VCCMON VCTERM SMA2 SMA1 VCTERM SMWP VCTERM VCTERM 3.3V RSVD SMA0 Datasheet System Bus Signal Name Location VCTERM VCTERM THRMALERT# VSSMON VCTERM VCCMON VCTERM...
  • Page 54 Pinout Specifications Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 2 of 15) Pin Name SMSD SMSC VCTERM VCTERM D002# D000# VCTERM D035# D033# VCTERM VCTERM D073# D070# VCTERM D099# D097# VCTERM D004# D003# D005# D037# D034# System Bus Signal Name Location SMSD...
  • Page 55 Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 3 of 15) Pin Name D036# D065# D066# D064# D102# D098# D104# VCTERM D001# STBP0# VCTERM D010# D040# VCTERM STBP2# D039# VCTERM D067# STBP4# VCTERM D074# D096# VCTERM STBP6# D100# D007# Datasheet System Bus Signal Name...
  • Page 56 Pinout Specifications Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 4 of 15) Pin Name STBN0# D006# D045# STBN2# D044# D068# STBN4# D069# D106# STBN6# D103# VCTERM D014# VCTERM D008# D015# VCTERM D038# D041# VCTERM D043# D071# VCTERM D072# D079# VCTERM D101#...
  • Page 57 Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 5 of 15) Pin Name VCTERM D107# D011# D012# D009# D042# D032# D046# D075# D076# D077# D111# D105# D109# VCTERM D013# DEP01# VCTERM DEP00# DEP04# VCTERM DEP05# D047# VCTERM D078# Datasheet System Bus Signal Name Location...
  • Page 58 Pinout Specifications Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 6 of 15) Pin Name DEP09# VCTERM DEP08# DEP12# VCTERM DEP13# D110# D016# D018# D049# D050# D083# D080# D117# D114# VCTERM D017# VCTERM D019# D021# VCTERM System Bus Signal Name Location DEP9# VCTERM...
  • Page 59 Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 7 of 15) Pin Name D053# D056# VCTERM D052# D081# VCTERM D088# D082# VCTERM D112# D116# VCTERM D113# D020# STBP1# D028# D048# STBP3# D051# D084# STBP5# D086# D118# STBP7# D115# VCTERM D023# Datasheet System Bus...
  • Page 60 Pinout Specifications Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 8 of 15) Pin Name STBN1# VCTERM D022# D058# VCTERM STBN3# D055# VCTERM D091# STBN5# VCTERM D085# D127# VCTERM STBN7# D119# D027# D024# D026# D054# D061# D057# D087# D093# D095# D122# D125#...
  • Page 61 Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 9 of 15) Pin Name D120# VCTERM D025# VCTERM D029# D031# VCTERM D063# D060# VCTERM D059# D092# VCTERM D089# D090# VCTERM D124# D126# VCTERM D121# D030# DEP03# DEP02# DEP06# DEP07# D062# D094# DEP11# DEP10#...
  • Page 62 Pinout Specifications Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 10 of 15) Pin Name DEP14# DEP15# D123# VCTERM A005# VCTERM A009# A018# VCTERM A016# VCTERM A028# BNR# VCTERM A027# A048# VCTERM A042# VCTERM A004# A010# A003# A015# A020# A019# A031# System Bus...
  • Page 63 Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 11 of 15) Pin Name A038# A029# A045# A047# A040# A006# A012# A014# A021# A026# A022# A037# A032# A030# A044# A046# A041# A007# A013# A008# A017# A024# A025# A034# A036# Datasheet System Bus Signal Name Location...
  • Page 64 Pinout Specifications Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 12 of 15) Pin Name A035# A039# A049# A043# ID3# A011# DRDY0# DBSY0# A023# SBSY0# BINIT# A033# DBSY1# DRDY1# AP1# AP0# ID1# ID5# ID9# RS2# HIT# HITM# DEFER# BR2# System Bus Signal Name Location...
  • Page 65 Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 13 of 15) Pin Name ADS# BERR# BPM5# ID2# ID7# IDS# DBSY# DRDY# TND# SBSY1# N/C# BPM3# BPM1# ID0# ID4# ID8# RS1# REQ2# REQ5# GSEQ# BR1# RESET# Datasheet System Bus Signal Name Location AB19 ADS#...
  • Page 66 Pinout Specifications Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 14 of 15) Pin Name BPM0# BPM4# TERMB ID6# RS0# REQ0# REQ3# SBSY# LOCK# BPRI# TRST# BPM2# PMI# TERM OUTEN RSP# INIT# REQ1# REQ4# TRDY# BR0# BR3# PPODGD# LINT0 LINT1 System Bus Signal Name...
  • Page 67 Table 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 15 of 15) Pin Name TUNER[2] BCLKp CPUPRES# IGNNE# THRMTRIP# TUNER[1] BCLKn PWRGOOD A20M# FERR# Datasheet System Bus Signal Name Location AG02 AG03 AG04 AG05 AG06 AG07 AG08 AG09 AG10 AG11 AG12 AG13 AG14...
  • Page 68 Pinout Specifications Datasheet...

  • Page 69: Mechanical Specifications

    This chapter provides the mechanical specifications of the Itanium 2 processor. Mechanical Dimensions The Itanium 2 processor package is comprised of an interposer, a processor package substrate, and an integrated heat spreader (IHS), as illustrated in socket and the power pod and contains 611 pins which are positioned in a 25 x 28 grid. The IHS, which is mounted on the top surface of the processor package substrate, efficiently transfers the heat generated by the die to its surface.

  • Page 70: Itanium ® 2 Processor Package

    Mechanical Specifications ® Figure 4-2. Itanium 2 Processor Package 48.26 IHS Height (See Note) Substrate Height (See Note) 1.43 0.00 2.03 Ø 611 x 0.305 Pins All dimensions are measured in mm. Not to scale. NOTE: Processor 900 MHz (1.5 MB) 1.0 GHz (3 MB) 1.3 GHz (3 MB) 1.4 GHz (4 MB)

  • Page 71: Itanium ® 2 Processor Package Power Tab

    ® Figure 4-3. Itanium 2 Processor Package Power Tab 2.48 12x 2.92 12x 0.86 10x 1.15 46.96 2x 16.10 2.98 46.96 All dimensions are measured in mm. Not to scale. Datasheet 2x R1.20 2x 25.85 12x 38.76 42.46 45.00 90.00 Top View 2x 9.10 2x 12.91...

  • Page 72: Package Marking

    Country of origin • 2D Matrix Mark (on Itanium 2 processor [1.30 GHz, 1.40 GHz, 1.50 GHz, 1.60 GHz], Itanium 2 (9 MB) class of processors and Montecito class of processors only. Not included on the Itanium 2 [900 MHz, 1.0 GHz] processor).

  • Page 73: Processor Bottom-Side Marking Placement On Interposer

    Figure 4-5. Processor Bottom-Side Marking Placement on Interposer NOTE: 2D Matrix Mark only present on Itanium 2 processor (6 MB), Itanium 2 processor (4 MB) and Itanium 2 processor (1.3 GHz, 3 MB). Datasheet AH25 Mechanical Specifications Laser Mark including...
  • Page 74 Mechanical Specifications Datasheet...

  • Page 75: Thermal Specifications

    This chapter provides a description of the thermal features relating to the Itanium 2 processor. Thermal Features The Itanium 2 processor has an internal thermal circuit which senses when a certain temperature is reached on the processor core. This circuit is used for controlling various thermal states. In addition, an on-chip thermal diode is available for use by the thermal sensing device on the Itanium 2 processor.

  • Page 76: Enhanced Thermal Management

    5.1.2 Enhanced Thermal Management ETM is a new feature that has been added to the Itanium 2 processor. ETM uses a thermal sensing device on the die to monitor a thermal entry point, indicating dangerous operation exceeding the thermal specification. Once the thermal sensing device observes the temperature rise above the thermal entry point, the processor will enter a low power mode of execution and notify the system by sending a Correctable Machine Check Interrupt (CMCI).

  • Page 77: Itanium ® 2 Processor Package Thermocouple Location

    Thermal Specifications ® Figure 5-2. Itanium 2 Processor Package Thermocouple Location 24.13 45.00 Thermocouple Location All dimensions are measured in mm. Not to scale. 001103a Datasheet...
  • Page 78 Thermal Specifications Datasheet...

  • Page 79: System Management Feature Specifications

    The thermal sensing device is connected to the anode and cathode of the Itanium 2 processor on-die thermal diode. SMBus implementation on the Itanium 2 processor uses the clock and data signals as defined by SMBus specifications.

  • Page 80: Logical Schematic Of Smbus Circuitry

    NOTE: 1. Actual implementation may vary. 2. For use in general understanding of the architecture. 3.3V Processor Information Scratch EEPROM SMWP SMSD SMSC Stuffing Options Intel ® Itanium ® 2 Processor Core THERMDA THERMDC STBY Thermal Sensing Device ALERT THRMALERT# 3.3V...

  • Page 81: Smbus Device Addressing

    3.3V (‘1’) for the processor information ROM. The “XX” bits are defined by the processor socket via the SMA0 and SMA1 pins on the Itanium 2 processor connector. These address pins have a weak pull-down (10 kΩ) to ensure that the memory components are in a known state in systems which do not support the SMBus, or only support a partial implementation.

  • Page 82: Processor Information Rom

    System Management Feature Specifications Table 6-3. EEPROM SMBus Addressing on the Itanium Upper Address Address (Hex) Bits 7–4 A0h/A1h 1010 A2h/A3h 1010 A4h/A5h 1010 A6h/A7h 1010 A8h/A9h 1010 AAh/ABh 1010 ACh/ADh 1010 AEh/AFh 1010 NOTES: 1. Though this addressing scheme is targeted for up to four-way MP systems, more processors can be supported by using a multiplexed (or separate) SMBus implementation.
  • Page 83 Table 6-4. Processor Information ROM Format (Sheet 2 of 4) Offset/ # of Section Bits Feature Data Address Other Data Address Reserved Checksum Processor S-spec Number Sample/Production Reserved Checksum Core Architecture Revision Processor Core Family Processor Core Model Processor Core Stepping Reserved Maximum Core Frequency Maximum System Bus...
  • Page 84 • 3Ah = 2 or 3 Add up by byte and take 2’s complement Itanium 2 (900 MHz, 1.0 GHz) = 80542KC. Itanium 2 processor (1.30 GHz -1.66 GHz) = 80543KC: • 3Eh = “8” • 3Fh = “0” • 40h = “5”...

  • Page 85: Scratch Eeprom

    Also available on the SMBus interface on the processor is an EEPROM which may be used for other data at the system vendor’s discretion (Intel will not be using the scratch EEPROM). The data in this EEPROM, once programmed, can be write-protected by asserting the active-high SMWP signal.

  • Page 86: Thermal Sensing Device

    These values can be individually programmed on the thermal sensor. If the measured temperature equals or exceeds the alarm threshold value, the appropriate bit is set in the thermal sensing device status register, which is also brought out to the Itanium 2 processor system bus via the Table 6-7, ‘S’...

  • Page 87: Thermal Sensing Device Supported Smbus Transactions

    THRMALERT# signal (see register values need to be programmed into the thermal sensing device via the SMBus. It is recommended that the upper thermal reference threshold byte (provided in the processor information ROM) be used for setting the upper threshold value in the alarm register. When polling the thermal sensing device on the processor to read the processor temperatures, it is recommended that the polling frequency be every 0.5 to 1 second.

  • Page 88: Thermal Sensing Device Registers

    System Management Feature Specifications Table 6-13. Command Byte Bit Assignment Register RESERVED RESERVED RESERVED RRHL RRLL RESERVED RESERVED WRHL WRLL OSHT RESERVED All of the commands are for reading or writing registers in the thermal sensor except the one-shot command (OSHT). The one-shot command forces the immediate start of a new voltage-to- temperature conversion cycle.

  • Page 89: Thermal Limit Registers

    If the diode thermal value equals or exceeds one of its limits, then its alarm bit in the status register is triggered. This indication is also brought out to the Itanium 2 processor system bus via the THRMALERT# signal.

  • Page 90: Conversion Rate Register

    System Management Feature Specifications 6.7.5 Conversion Rate Register The contents of the conversion rate register determine the nominal rate at which analog-to-digital conversions happen when the thermal sensing device is in auto-convert mode. the mapping between conversion rate register values and the conversion rate. As indicated in Table 6-16, the conversion rate register is set to its default state of 02h (0.25 Hz nominally) when the thermal sensing device is powered-up.

  • Page 91: A.1.5 Asz[1:0]# (I/O)

    ADS# assertion. These signals must connect the appropriate pins of all agents on the Itanium 2 processor system bus. The A[49:27]# signals are parity-protected by the AP1# parity signal, and the A[26:3]# signals are parity-protected by the AP0# parity signal.

  • Page 92: A-2 Effective Memory Type Signal Encoding

    BCLKp and BCLKn on the signals that are using the common clock latched protocol. BCLKp and BCLKn indirectly determine the internal clock frequency of the Itanium 2 processor. Each Itanium 2 processor derives its internal clock by multiplying the BCLKp and BCLKn frequency by a ratio that is defined and allowed by the power-on configuration.

  • Page 93: A-3 Special Transaction Encoding On Byte Enables

    For memory or I/O transactions, the byte-enable signals indicate that valid data is requested or being transferred on the corresponding byte on the 128-bit data bus. BE[0]# indicates that the least significant byte is valid, and BE[7]# indicates that the most significant byte is valid. Since BE[7:0]# specifies the validity of only 8 bytes on the 16 byte wide bus, A[3]# is used to determine which half of the data bus is validated by BE[7:0]#.

  • Page 94: Binit# (I/O)

    Signals Reference A.1.10 BINIT# (I/O) If enabled by configuration, the Bus Initialization (BINIT#) signal is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state machines are reset. All agents reset their rotating IDs for bus arbitration to the same state as that after reset, and internal count information is lost.

  • Page 95: A-5 Br0# (I/O), Br1#, Br2#, Br3# Signals For 2P Rotating Interconnect

    Table A-4. BR0# (I/O), BR1#, BR2#, BR3# Signals for 4P Rotating Interconnect Bus Signal BREQ[0]# BREQ[1]# BREQ[2]# BREQ[3]# Table A-5. BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect Bus Signal BREQ[0]# BREQ[1]# BREQ[2]# BREQ[3]# During power-on configuration, the priority agent must assert the BR[0]# bus signal. All symmetric agents sample their BR[3:0]# pins on asserted-to-deasserted transition of RESET#.

  • Page 96: Ccl# (I/O)

    A.1.17 CPUPRES# (O) CPUPRES# can be used to detect the presence of a Itanium 2 processor in a socket. A ground indicates that a Itanium 2 processor is installed, while an open indicates that a Itanium 2 processor is not installed.

  • Page 97: A-7 Did[9:0]# Encoding

    A.1.22 DBSY_C2# (O) DBSY# is a copy of the Data Bus Busy signal. This copy of the Data Bus Busy signal (DBSY_C2#) is an output only. A.1.23 DEFER# (I) The DEFER# signal is asserted by an agent to indicate that the transaction cannot be guaranteed in- order completion.

  • Page 98: Dps# (I/O)

    The Data Size (DSZ[1:0]#) signals are transferred on REQb[4:3]# signals in the second clock of the Request Phase by the requesting agent. The DSZ[1:0]# signals define the data transfer capability of the requesting agent. For the Itanium 2 processor, DSZ# = 01, always. A.1.32...

  • Page 99: A-8 Extended Function Signals

    Table A-8. Extended Function Signals Extended Function Signal EXF[4]# EXF[3]# EXF[2]# EXF[1]# EXF[0]# A.1.33 FCL# (I/O) The Flush Cache Line (FCL#) signal is driven to the bus on the second clock of the Request Phase on the A[6]# pin. FCL# is asserted to indicate that the memory transaction is initiated by the global Flush Cache (FC) instruction.

  • Page 100: A-9 Length Of Data Transfers

    Signals Reference A.1.39 IGNNE# (I) IGNNE# is ignored in the Itanium 2 processor system environment. A.1.40 INIT# (I) The Initialization (INIT#) signal triggers an unmasked interrupt to the processor. INIT# is usually used to break into hanging or idle processor states. Semantics required for platform compatibility are supplied in the PAL firmware interrupt service routine.

  • Page 101: Lint[1:0] (I)

    NMI, a non-maskable interrupt.Both signals are asynchronous inputs. A.1.45 LOCK# (I/O) LOCK# is never asserted or sampled in the Itanium 2 processor system environment. A.1.46 NMI (I) The NMI signal is the Non-maskable Interrupt signal. Asserting NMI causes an interrupt with an internally supplied vector value of 2.

  • Page 102: A-10 Transaction Types Defined By Reqa#/Reqb# Signals

    Signals Reference All receiving agents observe the REQ[5:0]# signals to determine the transaction type and participate in the transaction as necessary, as shown in Table A-10. Transaction Types Defined by REQa#/REQb# Signals Transaction Deferred Reply Reserved Interrupt Acknowledge Special Transactions Reserved Reserved Interrupt...

  • Page 103: A.1.53 Rs[2:0]# (I)

    A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This definition allows parity to be high when all covered signals are high. A.1.53 RS[2:0]# (I) The Response Status (RS[2:0]#) signals are driven by the responding agent (the agent responsible for completion of the transaction).

  • Page 104: Stbn[7:0]# And Stbp[7:0]# (I/O)

    The Test Clock (TCK) signal provides the clock input for the IEEE 1149.1 compliant TAP. A.1.61 TDI (I) The Test Data In (TDI) signal transfers serial test data into the Itanium 2 processor. TDI provides the serial input needed for IEEE 1149.1 compliant TAP. A.1.62 TDO (O) The Test Data Out (TDO) signal transfers serial test data out from the Itanium 2 processor.

  • Page 105: A.2 Signal Summaries

    Table A-12. Output Signals (Sheet 1 of 2) Name CPUPRES# DBSY_C1# DBSY_C2# DRDY_C1# DRDY_C2# FERR# Datasheet Table A-15 list attributes of the Itanium 2 processor output, input, and I/O Active Level Clock Signal Group — BCLKp BCLKp BCLKp BCLKp Asynchronous...

  • Page 106: Input Signals

    Signals Reference Table A-12. Output Signals (Sheet 2 of 2) Name SBSY_C1# SBSY_C2# THRMTRIP# THRMALERT# Table A-13. Input Signals Name BPRI# BR1# BR2# BR3# BCLKp BCLKn D/C# DEFER# DHIT# GSEQ# ID[9:0]# IDS# INIT# INT (LINT0) IP[1:0]# NMI (LINT1) RESET# RS[2:0]# RSP# PMI# PWRGOOD...

  • Page 107: Input/Output Signals (Single Driver)

    Table A-14. Input/Output Signals (Single Driver) Name A[49:3]# ADS# AP[1:0]# ASZ[1:0]# ATTR[3:0]# BE[7:0]# BR0# BPM[5:0]# CCL# D[127:0]# DBSY# D/C# DEN# DEP[15:0]# DID[9:0]# DRDY# DPS# DSZ[1:0]# EXF[4:0]# FCL# LEN[2:0]# LOCK# OWN# REQ[5:0]# SBSY# SPLCK# STBn[7:0]# STBp[7:0]# WSNP# Table A-15. Input/Output Signals (Multiple Driver) Name BNR# BERR#...
  • Page 108 Signals Reference Datasheet...

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