Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet page 122

B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
3:0
122
0/1/0–2/PCI
D0–D1h
0002h
RWS, RWS-V
16 bits
0h
Reset RST/
Attr
Value PWR
Powerg
RWS 2h
ood
Processor Configuration Registers
Description
Target Link Speed (TLS)
For Downstream ports, this field sets an upper limit on link
operational speed by restricting the values advertised by the
upstream component in its training sequences.
Defined encodings are:
0001 = 2.5 Gb/s Target Link Speed
0010 = 5Gb/s Target Link Speed
All other encodings are reserved.
If a value is written to this field that does not correspond to a
speed included in the Supported Link Speeds field, the result is
undefined.
The Reset Value of this field is the highest link speed supported by
the component (as reported in the Supported Link Speeds field of
the Link Capabilities Register) unless the corresponding platform /
form factor requires a different Reset Value.
For both Upstream and Downstream ports, this field is used to set
the target compliance mode speed when software is using the
Enter Compliance bit to force a link into compliance mode.
Datasheet, Volume 2